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max64180 hd h.264 codec revision 1.1: 06/04/12 doc. no: 2001_ds confidential data sheet for pricing, delivery, and ordering informati on, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. maxim integrated products
revision 1.1 6/4/12 page # confidential maxim integrated products 120 san gabriel drive sunnyvale, ca 94086 united states 408-737-7600 www.maxim-ic.com copyright ? 2012 maxim integrated products maxim cannot assume responsibilit y for use of any circuitry ot her than circuitry entirely embodied in a maxim product. maxim re tains the right to make changes to its products or specifications to improve performance, reliability or manufac turability. all infor mation in this document, including descriptions of features, functions, performance, technical sp ecifications and availability, is subjec t to change without notice at any time. while the information furnis hed herein is held to be accurate and reliable, no responsibilit y will be assumed by maxim for its use. furthermore, the information contai ned herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. maxim products are not intended for use in life support products where failure of a maxim pr oduct could reasonably be expected to result in death or personal injury. anyone using a maxim product in such an application without express written consent of an o fficer of maxim does so at their own risk, and agrees to fully indemnify maxim for any damages that may result from such use or sale. is a registered trademark of maxim integrated products, inc. all other products or service names used in this publication ar e for identification purposes only, and may be trademarks or reg istered trademarks of their respective companies. all other trademarks or registered trademarks mentioned herein are the property of th eir respective holders.
revision 1.1 6/4/12 page 5 confidential max64180 data sheet contents contents revision history....... ......................................................................................... ........... 13 1 introduction ............... ............................................................................. ........... 15 1.1 features .................................................................................................................... ....... 16 1.2 applications ................................................................................................................ ...... 16 1.3 additional documentation................................................................................................. 16 1.4 trademark information ..................................................................................................... 17 2 general description ............. .................................................................. ........... 19 2.1 features .................................................................................................................... ....... 20 2.2 general overview ............................................................................................................ .22 2.2.1 video i/o ports .................................................................................................... 22 2.2.2 video input processor ......................................................................................... 22 2.2.3 video output processor....................................................................................... 22 2.2.4 video and audio multimedia engines .. ................................................................ 23 2.2.5 audio interface..................................................................................................... 23 2.2.6 memory interface................................................................................................. 23 2.2.7 arm processor.................................................................................................... 23 2.2.8 aes and sha hardware a cceleration.......... ................ ................. ............ ..........24 2.3 peripheral interfaces ....................................................................................................... .24 2.3.1 usb 2.0 interface ................................................................................................ 24 2.3.2 serial interfaces................................................................................................... 24 3 functional description .... ...................................................................... ........... 25 3.1 video subsystem............................................................................................................. .26 3.1.1 video ports .......................................................................................................... 27 3.1.2 video control signals .......................................................................................... 28 3.1.3 video clocks........................................................................................................ 29 3.1.4 video i/o power domains ................................................................................... 29 3.1.5 video input processor (vip) ................................................................................ 30 3.1.6 video output processor (vop)............ ................................................................ 32 3.2 audio subsystem............................................................................................................. .33 3.2.1 audio group signals............................................................................................ 33 3.2.2 audio clocks........................................................................................................ 33 3.3 encoder subsystem ......................................................................................................... 34 3.4 host interface .............................................................................................................. ..... 35 3.4.1 host interface connections ................................................................................. 35 3.4.2 host interface signals.......................................................................................... 36 3.5 memory interface............................................................................................................ .. 37 3.5.1 ddr2 sdram connections ................................................................................ 37 3.6 serial interfaces........................................................................................................... ..... 38 3.6.1 uart interface .................................................................................................... 38 3.6.2 two-wire (twi) interface..................................................................................... 39 3.6.3 spi interface ........................................................................................................ 39 3.6.4 pulse width modulators....................................................................................... 40 3.6.4.1 serial i/o pad programmable features................................................. 40
revision 1.1 6/4/12 page 6 confidential max64180 data sheet contents 3.7 usb 2.0 high-speed interface ......................................................................................... 41 3.7.1 physical layer (phy)........................................................................................... 42 3.7.2 usb controller..................................................................................................... 44 3.8 high-speed bitstream ....................................................................................................... 4 7 3.8.1 bitstream signals................................................................................................. 48 3.8.2 bitstream mode.................................................................................................... 48 3.8.3 clock plus enable mode...................................................................................... 49 3.9 reset logic................................................................................................................ ...... 50 3.9.1 power-on reset .................................................................................................. 50 3.9.2 watchdog reset .................................................................................................. 50 3.9.3 software chip reset............................................................................................ 50 3.9.4 reset timing........................................................................................................ 51 3.10 clocks and phase lock loops (plls).............................................................................. 52 3.10.1 clock and pll inputs........................................................................................... 52 3.10.2 phase lock loops ............................................................................................... 53 3.10.3 video and audio clocks....................................................................................... 53 3.10.3.1 video input clocks............................................................................... 54 3.10.3.2 video output clocks ............................................................................ 54 3.10.3.3 audio clocks.... .................................................................................... 54 3.11 device configuration ....................................................................................................... .55 3.11.1 reset ................................................................................................................... 5 5 3.11.2 boot mode for the mmes and the arm . .............................................................. 55 3.11.3 api configuration................................................................................................. 56 3.11.4 pin muxing ...........................................................................................................56 3.11.5 debug mode ........................................................................................................ 56 3.12 oscillator connections..................................................................................................... .56 3.12.1 crystal connected to usb_xin and usb_xo pins ............................................ 56 3.12.2 crystal and external clock connected to external clk_in pin .......................... 57 4 power supply considerations ... ........................................................... ........... 59 4.1 power supply sequencing ........................... .................................................................... 59 4.2 power supply ................................................................................................................ ... 60 5 electrical specifications......... ............................................................... ........... 61 5.1 operating parameters ...................................................................................................... 61 5.2 dc characteristics.......................................................................................................... .. 62 5.3 ac timing ................................................................................................................... ...... 63 5.3.1 video interface ac timi ng ................................................................................... 64 5.3.2 audio interface ac timing ................................................................................... 66 5.3.3 host interface ac timing 68 5.3.4 ddr2 sdram interface ac timing .................................................................... 72 5.3.5 spi/bitstream interface ac timing ...................................................................... 72 6 pin definitions ........... ............................................................................. ........... 81 6.1 max64180 pin configuration?248-pin ctbga . ............................................................. 81 6.2 signal definitions .......................................................................................................... .... 86 6.3 pin identifications ......................................................................................................... .... 87 6.4 pin muxing .................................................................................................................. ...... 88 6.4.1 audio signal group..............................................................................................90
revision 1.1 6/4/12 page 7 confidential max64180 data sheet contents 6.4.2 video port 0 signal group ................................................................................... 91 6.4.3 video port 2 signal group ................................................................................... 92 6.4.4 host signal group ............................................................................................... 93 6.4.5 ddr2 sdram signal group ............................................................................... 94 6.4.6 usb signal group ............................................................................................... 96 6.4.7 uart signal group ............................................................................................. 96 6.4.8 spi/bitstream signal group................................................................................. 97 6.4.9 twi signal group ................................................................................................ 97 6.4.10 pwm signal group ..............................................................................................98 6.4.11 gpio signal group..............................................................................................98 6.4.12 jtag signal group............................................................................................100 6.4.13 configuration .....................................................................................................100 6.4.14 clock..................................................................................................................10 1 6.4.15 reset .................................................................................................................101 6.4.16 power and ground pins.....................................................................................102 6.5 pin list by power group .................................................................................................105 6.5.1 hookup recommendations when interfac es are unused ................................106 7 package information........ ...................................................................... .......... 111 7.1 package outline?248-pin ctbga, 10mm 10 mm...................................................... 112 7.2 package diagram ...... ..................................................................................................... 11 2 7.3 thermal data ................................................................................................................ .. 113 7.3.1 thermal resistance........................................................................................... 113 7.4 marking ..................................................................................................................... ...... 114 8 ordering information .............. ............................................................... ..........115
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revision 1.1 6/4/12 page 9 confidential max64180 data sheet contents figures figure 1-1. max64180 block di agram ....................................................................................... 15 figure 3-2. functional block diagram .............. .......................................................................... 25 figure 3-3. video subsystem ................................................................................................... .. 26 figure 3-4. video input proc essor ............................................................................................. .30 figure 3-5. video input proce ssing data flow ........................................................................... 31 figure 3-6. video output processing data fl ow ........................................................................ 32 figure 3-7. audio group signals ............................................................................................... .33 figure 3-8. host interface connections...................................................................................... 35 figure 3-9. ddr2 sdram connections for 512mb 16-bit......................................................... 37 figure 3-10. uart module to interface signal mapping .............................................................. 38 figure 3-11. twi module to in terface signal mapping .................................................................39 figure 3-12. spi module to in terface signal mapping.................................................................. 39 figure 3-13. usb interface block diagram .................................................................................. 41 figure 3-14. usb controller ................................................................................................... ...... 44 figure 3-15. high-speed bitstream signals ....... .......................................................................... 47 figure 3-16. receive with bitstream clock and bitstream enable timing.................................... 49 figure 3-17. reset timing ..................................................................................................... ....... 51 figure 3-18. clocking structure ............................................................................................... ..... 52 figure 3-19. video and audio clocks ................. .......................................................................... 53 figure 3-20. clock configuration with an extern al crystal ........................................................... 56 figure 3-21. clock configuration with an extern al crystal ........................................................... 57 figure 3-22. clock configuration with an extern al crystal ........................................................... 58 figure 4-23. power supply sequencing ............. .......................................................................... 59 figure 5-24. video interface timing ................ ........................................................................... .. 64 figure 5-25. standard audio timing ............................................................................................ .66 figure 5-26. 16-, 20-bit left justified audio waveform ................................................................ 66 figure 5-27. audio interface timing ................ ........................................................................... .. 67 figure 5-28. host interface timing ............................................................................................ ... 68 figure 5-29. host direct memory access (dma) timing ............................................................ 69 figure 5-30. host wait timing ................................................................................................. ..... 69 figure 5-31. host interrupt timing............................................................................................ .... 70 figure 5-32. bitstream timing with an external clo ck and external data master ........................ 73 figure 5-33. bitstream timing with an external clo ck and internal data master ......................... 75 figure 5-34. bitstream timing with an internal clock and external data master ......................... 77 figure 5-35. bitstream timing with an internal clock and internal data master .......................... 79 figure 6-36. max64180 soc signal positions (t op view) ........................................................... 81 figure 6-37. upper-left quadrant .............................................................................................. .. 82 figure 6-38. upper-right quadrant............................................................................................. .83
revision 1.1 6/4/12 page 10 confidential max64180 data sheet contents figure 6-39. bottom-left quadrant............................................................................................. .. 84 figure 6-40. bottom-right quadrant ............................................................................................ 85 figure 7-41. max64180 248-pi n ctbga package physical drawing ....................................... 112 figure 7-42. thermal resistance ............................................................................................... 113 figure 7-43. max64180 marking................................................................................................ 1 14
revision 1.1 6/4/12 page 11 confidential max64180 data sheet contents tables table 2-1. max64180 soc features ........................................................................................ 19 table 2-2. video input formats ....................... ......................................................................... .22 table 2-3. video output formats ..............................................................................................2 3 table 3-4. video input signals for video port 0 and video port 2............................................. 27 table 3-5. video output connections: video port 2.................................................................. 28 table 3-6. video control signal groups.................................................................................... 28 table 3-7. supported encoding and decoding modes.............................................................. 34 table 3-8. host interface pin description.................................................................................. 36 table 3-9. serial i/o interfaces .............................................................................................. ... 38 table 3-10. uart baud rate frequencies................................................................................. 38 table 3-11. bitstream signals ................................................................................................. .... 48 table 3-12. boot modes ........................................................................................................ ...... 55 table 3-13. crystal specifications ............................................................................................ ... 57 table 4-14. peak power supply currents for th e different power domains ............................... 60 table 5-15. recommended dc operating conditions................................................................ 61 table 5-16. dc characteristics ................................................................................................ ... 62 table 5-17. dc and ac characteristics for ddr2 sdram ........................................................ 62 table 5-18. standard definition video interfac e timing parameters .......................................... 64 table 5-19. high definition video interface timi ng parameters ................................................. 65 table 5-20. high-speed video interface timing parameters ...................................................... 65 table 5-21. audio interface timing parameters .......................................................................... 67 table 5-22. host interface timing parameters............................................................................ 70 table 5-23. bitstream timing parameters 1...... .......................................................................... 74 table 5-24. bitstream timing parameters 2...... .......................................................................... 76 table 5-25. bitstream timing parameters 3...... .......................................................................... 78 table 5-26. bitstream timing parameters 4...... .......................................................................... 80 table 6-27. signal group names................................................................................................ 87 table 6-28. pin muxing ........................................................................................................ ....... 88 table 6-29. audio signals ..................................................................................................... ......90 table 6-30. video port 0 signals.............................................................................................. ... 91 table 6-31. video port 2 signals.............................................................................................. ... 92 table 6-32. host signals ...................................................................................................... ....... 93 table 6-33. ddr2 sdram signals............................................................................................. 94 table 6-34. usb signals ....................................................................................................... ...... 96 table 6-35. uart signals...................................................................................................... .....96 table 6-36. serial peripheral interface/bitstrea m interface signals............................................ 97 table 6-37. two-wire interface signals ...................................................................................... 97 table 6-38. pulse width modulator signals ................................................................................ 98 table 6-39. gpio signals ...................................................................................................... .....98 table 6-40. gpio signals ...................................................................................................... .....99 table 6-41. additional gpio signals........................................................................................... 99 table 6-42. jtag signals ...................................................................................................... ...100 table 6-43. configuration signals ............................................................................................. 100 table 6-44. clock signals ..................................................................................................... ....101 table 6-45. reset signals ..................................................................................................... ....101
revision 1.1 6/4/12 page 12 confidential max64180 data sheet contents table 6-46. power pins ........................................................................................................ .....102 table 6-47. signal group names..............................................................................................10 5 table 6-48. hookup recommendations when inte rfaces are unused......................................107 table 7-49. case thermal conductivity data ........................................................................... 113 table 8-50. ordering information .............................................................................................. 115
revision 1.1 6/4/12 page 13 confidential max64180 data sheet revision history revision history this section describes the changes that were implemented in the data sheet. the changes are listed by revision. revision section description 1.1 revision history added table of abbreviations 1 changed video capture to video subsystem 2.2.1 moved video encoders and decoders section to chapter 3, section 3.3 encoder subsystem 3.1/3.2 renamed video interface to video subsys tem and audio interface to audio subystem 3.1.3/3.1.4 expanded abbreviations for video pi xel clock signal names, video input signals 3.3 moved section 2.2.1 to section 3.3 encoder subsystem 3.6.1 added that the uart debug port should al ways be connected to a serial terminal 3.6.4 added contact maxim technical support to progr am the device for drive strength. expanded ds as drive strength 3.8.1 expanded signal names in table 3-11 3.11.4 changed the title ?pin multiplexing, gpios? to pin muxing 4.2 added interface and power domain columns in table 4-14 5 expanded signal names in table 5-18, 5-19, 5-20, 5-22 6.4 modified text and removed pin entries that do not have multiple functions in table 6-28 6.4.4 removed figure 6-41 host connections 6 removed alt. and gpio columns in tables 6-29 through 6-45 7 changed thin flipchip ball grid to chip scale thin ball grid array 7.4 updated chip revision in marking from a0 to a1 8 updated ordering information MAX64180CXO+ 1.0 - first release
revision 1.1 6/4/12 page 14 confidential max64180 data sheet revision history abbreviations product-specific abbreviations are defined wherever ap plicable in the text. the most commonly used industry abbreviations applicable to the product are listed below. abbreviation description aac-lc advanced audio coding-low complexity adc analog to digital converter csbga chip scale ball grid array dma direct memory access eav end of active video fps frames per second gpio general purpose input/output hd high definition hdmi high definition multimedia interface hdr high dynamic range i 2 c intelligent interface controller i 2 s inter-ic sound ipc interconnecting and packagi ng electronic circuits isp image signal processing jedec joint electron de vice engineering council jpeg joint photographic experts group jtag joint test action group mjpeg moving joint photographic experts group mpeg-ts moving photographic experts group - transport stream pc personal computer pcm pulse code modulation pll phase lock loop phy physical interface pwm pulse width modulator ram random access memory rgb red green blue risc reduced instruction set computer rohs restriction of hazardous substances sav start of active video sd standard definition soc system-on-chip spi serial peripheral interface sms short message service snr signal to noise ratio twi two-wire interface usb universal serial bus uart universal asynchronous receiver/transmitter vga video graphics array
revision 1.1 6/4/12 page 15 confidential max64180 data sheet introduction 1 introduction the max64180 is a compression camera system-on-chip (soc) that enables high-quality internet video conferencing in environments with poor lighting a nd poor acoustics such as a home living room. it performs all video and audio processing required for an internet compression camera application, including video compression, image signal processing, audio ec ho cancellation, audio beamforming, audio noise suppression, and audio compression and decompression . combining high integration with advanced video processing, the max64180 soc is a cost-effective ideal solution for skype tvs, web, and ip camera applications. the max64180 is a highly integrated, low-power, h. 264 codec device that supports encoding of video up to 720p30 high definition (hd) resolu tion. it incorporates the latest video encodi ng capabilities including baseline, main, and high profile h.264 codec. it also supports a mjpeg codec and a mpeg-2 decoder. the max64180 contains a configurable hardware-based video subsystem, encoder subsystem, and an audio subsystem. it also includes an arm9 based on-c hip subsystem and a host of peripherals: usb, uart, pulse width modulator, and spi serial interfaces. figure 1-1. max64180 block diagram the video and audio subsystems comprise two real-time, programmable multimedia engines (mmes). one mme controls the video codecs and input output processors, while the other mme implements audio codecs. the video input processors (vips) in the video subsyst em accept video from exte rnal video ports, capture the video, and store it in memory. the vips support filtering, cropping, and rescaling the captured video. the video output processor (vop) streams video to output. 720p h.264 codec mjpeg codec video mme audio /system mme video input processor 0 sdram controller jtag host interface clocks ddr2 sdram stereo input audio analog-digital/ digital-analog 12mhz xtal aes/sha twi / spi pwm pwm uart usb 2.0 serial i /o serial i /o video input processor 1 i 2 s usb with phy video output processor bitstream i /f high-speed bitstream arm926 stereo output external host one video input and one video output or two video inputs bt.656 output bt.1120/ bt.656 input bt.1120/ bt.656 input
revision 1.1 6/4/12 page 16 confidential max64180 data sheet introduction 1.1 features high-quality video and audio encoding ? 720p30 video resolution ? h.264 main, baseline, and high profile tools ? spatial filter ? edge preserving noise reduction filter ? motion adaptive temporal filter flexible user configurations ? skype tv compatibility ? video input: resoluti on (scaling or cropping), frame rate, filtering ? compression: number of streams, bit rate, h.264 tools ? video output: compositing, scaling, cropping, frame rate, graphics overlay high level of system integration ? usb connection to the host device ? low power consumption ? 200mhz arm9 processor ? dedicated audio processor ? hardware acceleration for da ta security: advanc ed encryption standar d (aes) and secure hashing algorithm (sha) ? usb 2.0 including phy 1.2 applications ? television based internet video conferencing ? table pc based internet video conferencing 1.3 additional documentation in addition to the data sheet, the maxim web site of fers an extensive library of documentation, support files, and application materials spec ific to each device. visit and register as a member on the maxim web site to keep abreast of the latest innovations from research and development teams and the most current product and application documentation. th e address of the maxim web site is www.maxim-ic.com .
revision 1.1 6/4/12 page 17 confidential max64180 data sheet introduction 1.4 trademark information the following provides registered trademarks and trademarks listed in the max64180 data sheet. ? arm926 is a trademark of arm limited. ? skype is a trademark owned by skype limited, skype technologies, s.a.. ? spi ? is a trademark owned by motorola, inc. ?i 2 c is a registered trademark ow ned by nxp semiconductors n.v ., founded by philips electronics.
revision 1.1 6/4/12 page 18 confidential max64180 data sheet introduction
revision 1.1 6/4/12 page 19 confidential max64180 data sheet general description 2 general description the max64180 h.264 codec soc is a 720p30 codec. the chip encompasses an arm9 processor and a complete set of soc features as shown in table 2-1 . table 2-1. max64180 soc features features max64180 high definition (hd) h.264 codec 720p30 mpeg-2 decoder ? jpeg codec ? video: one video input/one video output: two 8-bit interfaces or two video inputs: one 16-bit interface, no output ? video input processors 2 video output processor 1 audio input port 1 audio output port 1 audio codecs ? high-speed bitstream i/o or spi ? embedded arm926-ej processor ? host slave mode operation ? usb 2.0 host or device ? 16-bit ddr2 sdram interface ? two-wire interface 1 uart 1 pulse width modulator 1 gpio, shared 20 gpio, dedicated 4
revision 1.1 6/4/12 page 20 confidential max64180 data sheet general description 2.1 features video inputs ?two advanced video input processors (vips) ? two 8-bit video ports: one input port, one bidirectional port ? 100mhz maximum speed i/o video processing ? spatial and temporal noise filtering ? edge enhancement ? statistic extraction for better compression ? vertical and horizontal scalars using 8-tap polyphase filters ? four field motion adaptive deinterlacer ? impulse noise filter video outputs ? one video output processor (vop) ? one 8-bit output ? 75mhz video output i/o video codecs ? high definition (hd) or standard definition (sd) h.264 codecs ? high, main, and baseline profiles support for resolutions up to 1280 x 720 at 30fps ? single hd or multi-stream encoding support ? h.264 codec up to level 4.1 ? programmable resolutions and frame rates ? video bit rates: 64kbps to 62.5mbps ? interlaced and frame capturing and encoding support ? mpeg-2 decoder ? hd and sd decoder ? real time mpeg-2 to h.264 transcoding ? multi-stream sd mpeg-2 decoding ? jpeg codec ? jpeg encoder and decoder ? hd or sd mjpeg support ? exchangeable image file format (exif) support
revision 1.1 6/4/12 page 21 confidential max64180 data sheet general description audio codecs ? high-fidelity, 2-channel audio coding-low complexity (aac-lc) codec ? mpeg-1/2 audio laye r ii codec (mp2) ? mpeg-1/2 audio layer i and iii decoder (mp1) ? pulse code modulation (pcm) format ? g.711, g.722, g.726 codec ? flexible bit rates and sample rates audio i/o ? one i 2 s audio input port and one i 2 s audio output port ? one sony/philips digital interface (s/pdif) output port integrated arm9 processor ? 240mhz general purpose processor ? 16kbyte data cache ? 16kbyte instruction cache ? 16kbyte scratch pad memory memory interface ? ddr2 sdram memory ? 16-bit data at 233mhz peripheral interfaces ? one two-wire interface port ? one uart port ? one pulse width modulator (pwm) ? high-speed bitstream i/o or one spi ? usb 2.0 port including the physical layer ? aes and sha hardware acceleration ? up to 24 gpio with four dedicated gpio pins power and voltage ? core voltage: 1.05v 5% ? sdram voltage: 1.8v 0.1v ? i/o voltages: 1.8v, 2.5v, 3.3v 5% ? on-chip audio, video phase lock loops (plls) driven from a single crystal ? typical power consumption is 950mw or less packaging ? 248-pin ctbga, 10x10mm, 0.5mm pitch, rohs compliant
revision 1.1 6/4/12 page 22 confidential max64180 data sheet general description 2.2 general overview the sections below provide a high-level descript ion on the various modules inside the max64180. 2.2.1 video i/o ports the max64180 includes two 8-bit video ports: video port 0 and video port 2. video port 0 is a dedicated 8- bit input port. video port 2 is a bidirectional 8-bit port that can be configured as an input or output. the two 8-bit ports can be combined to a single 16-bit input port. output is not available when both the ports are used as a single 16-bit input port. each video input supports independe nt clocks and synchronization sig nals. the clock frequency can be driven up to 75mhz to support non-standard video inpu ts including hd sensors with 8-bit interfaces. the max64180 receives video inputs in either bt.656 format on an 8-bit interface or bt.1120 format on a 16-bit interface. the max64180 can support the follo wing configurations with the two video i/o ports: 2.2.2 video input processor the two identical video input processors (vips) per form high-quality image scaling. the vips extract video statistics, which is used to improve the compre ssion efficiency of the co dec. the vips process the brightness, contrast, and gamma correction of the luma component and adjust the hue and saturation characteristics of the chroma component. the maximum pixel rate that the vips can process corresponds to the video input resolution of 1280 x 720p at 30 frames per seconds. 2.2.3 video output processor the video output processor (vop) performs high-qua lity image scaling of uncompressed video, overlays it with two graphic planes, performs gamma and chroma adjustment, overlays a hardware cursor, and outputs the combined video to a video port. each grap hic plane can be from 1 to 32 bits. graphic planes using less than eight bits use a look-up table (lut). table 2-2. video input formats video resolution frames per sec. ports 1600 x 1200 15 1 (8-bit) 1280 x 720 30 1 (8-bit) 640 x 480 30 1 (8-bit)
revision 1.1 6/4/12 page 23 confidential max64180 data sheet general description the video output can either be yuv 4:2: 2 or rgb format via an 8-bit interface . the rgb (8-8-8) output can be used for driving lcd displays. 2.2.4 video and audio multimedia engines the video multimedia engine (mme) is a proprietary reduced instruction set computer (risc) that is optimized for single cycle context switching and low power. the video mme controls all aspects of the vips, video cores, and the vop. the audio mme implements all audio codecs in firmware. 2.2.5 audio interface the audio interface contains a single audio input and single audio outpu t interface. the audio interface receives audio inputs from an i 2 s interface. the audio interface comprises: ? one i 2 s input, ? one i 2 s output, and ? one s/pdif output the i 2 s input shares a common clock, sample rate, and a common format with i 2 s audio output and s/pdif output. 2.2.6 memory interface the ddr2 sdram external memory device stores video , audio, and computational data during encoding or decoding video. the memory controller addresses 16-bit data at 233mhz. 2.2.7 arm processor the max64180 has an embedded arm9 processor that handles system functions and manages peripheral interfaces. the processor runs at speeds of up to 200mhz. the processor acts as the overall system controller and performs all system level functions. it is not used for any audio or video codec functions. table 2-3. video output formats video mode video output 8-bit yuv 4:2:2 rgb 8-8-8 over an 8-bit
revision 1.1 6/4/12 page 24 confidential max64180 data sheet general description 2.2.8 aes and sha ha rdware acceleration the max64180 design includes hardware acceleration for advanced encryption standard (aes) and secure hashing algorithm (sha). the aes accelera tor supports cbc (cipher block chaining), ctr (counter mode), ecb (electronic code book), a nd ccm (ctr with cbc) modes with 128-, 192-, and 256-bit keys for secure data storage and transmission. the sha accelerator supports the creation of 128-, 224-, and 256-bit digests for digital signatures and digital time stamps. 2.3 peripheral interfaces a number of peripheral interfac es for i/o control and system integration are described below. 2.3.1 usb 2.0 interface the high-speed usb 2.0 interface can operate as devi ce or host at speeds of up to 480mbps. the usb interface includes the physical layer. 2.3.2 serial interfaces the max64180 serial interfaces include uart fo r communication, pulse width modulator (pwm) for control, two-wire interface (twi) and serial peripheral interface (spi) for device control. the max64180 comprises four dedicated gene ral purpose input/output (gpio) pins and up to 20 shared gpio pins for system control. the shared gpio pi ns are multiplexed with other functions, which are available only when the primary or al ternate function is not being used. for example, if a design does not require an spi interface (see ?spi/bitstream interface ac timing? on page 72 ), the four pins dedicated to spi interface can be used as gpio pins.
revision 1.1 6/4/12 page 25 confidential max64180 data sheet functional description 3 functional description this section provides detailed informatio n on the architecture of the max64180. figure 3-2. functional block diagram 720p h.264 codec mjpeg codec video mme audio/system mme video input processor 0 sdram controller jtag host interface clocks ddr2 sdram stereo input audio analog-digital/ digital-analog 12mhz xtal aes/sha twi / spi pwm pwm uart usb 2.0 serial i /o serial i /o video input processor 1 i 2 s usb with phy video output processor bitstream i /f high-speed bitstream arm926 stereo output external host one video input and one video output or two video inputs bt.656 output bt.1120/ bt.656 input bt.1120/ bt.656 input
revision 1.1 6/4/12 page 26 confidential max64180 data sheet functional description 3.1 video subsystem the video subsystem consists of two video input pr ocessors (vips) and one video output processor (vop). the vip captures input vide o while the vop outputs video from the chip. the video input signals are routed through two video ports to the vips. the max64180 provides two dedicated video i/o ports: video port 0 and video port 2. the ports can receive either two 8-bit video inputs in bt.656 format or a combined 16-bit video input in bt.1120 format for hd video. figure 3-3. video subsystem the max64180 can be configured to support a maximum of two inputs or one input and one output. typical scenarios for video input and output include: ? one 8-bit input, one 8-bit output ? two 8-bit inputs, no output ? one 16-bit input, no output video port 0 is a dedicated input port. video port 2 can be reconfigured in the system depending on the system use-case since the port can be either an input or an output port. memory controller vip1 vip0 vop 8-bit video input/output 8-bit video input from memory rgb or yuv 4:2:2 high definition h.264 codec high definition mpeg2 decoder high definition jpeg codec vid0_d[7:0] vid2_d[7:0] 16-bit data video module memory from memory
revision 1.1 6/4/12 page 27 confidential max64180 data sheet functional description 3.1.1 video ports ta b l e 3 - 4 shows the video input connections for video port 0 which can be used only as an input port. ta b l e 3 - 4 and ta b l e 3 - 5 show the video input connections for video port 2, which can be used either as an input or output port. table 3-4. video input signals for video port 0 and video port 2 pin 8-bit video port 0 8-bit video port 2 16-bit video ports 0 and 2 vid0_d0 video in bit 0 - video in bit 0 vid0_d1 video in bit 1 - video in bit 1 vid0_d2 video in bit 2 - video in bit 2 vid0_d3 video in bit 3 - video in bit 3 vid0_d4 video in bit 4 - video in bit 4 vid0_d5 video in bit 5 - video in bit 5 vid0_d6 video in bit 6 - video in bit 6 vid0_d7 video in bit 7 - video in bit 7 vid0_field video in field - video in field vid0_hsync horizontal sync/hvalid signal 0 - horizontal sync/hvalid signal 0 vid0_vsync vertical sync/vvalid signal 0 - vertical sync/vvalid signal 0 vid2_d0 - video in bit 0 video in bit 8 vid2_d1 - video in bit 1 video in bit 9 vid2_d2 - video in bit 2 video in bit 10 vid2_d3 - video in bit 3 video in bit 11 vid2_d4 - video in bit 4 video in bit 12 vid2_d5 - video in bit 5 video in bit 13 vid2_d6 - video in bit 6 video in bit 14 vid2_d7 - video in bit 7 video in bit 15 vid2_field - video in field - vid2_hsync - horizontal sync/hvalid signal 2 - vid2_vsync - vertical sync/vvalid signal 2 -
revision 1.1 6/4/12 page 28 confidential max64180 data sheet functional description 3.1.2 video control signals the max64180 has two sets of video control signals: video control 0 (vco) and video control 2 (vc2). each video control signal group cons ists of horizontal sync, vertical sync, and field signals, which can also be used as line valid and frame valid signals. when the output port is active, the video output processor is configured to output the correct video timing appropriate to the interface. the video control sign als vc0 and vc2 can be assigned to any of the video ports with the following restriction: ? video control signal group vc0 is always associ ated with the power plane fo r video port 0. video control signal group vc2 is associated with the power plane for video port 2. if the power planes are connected to different power sources, the video control signal group must be assigned to a video port in the same power plane. see ?video i/o power domains,? page 29. table 3-5. video output connections: video port 2 pin 8-bit video port 2 vid2_d0 video out bit 0 vid2_d1 video out bit 1 vid2_d2 video out bit 2 vid2_d3 video out bit 3 vid2_d4 video out bit 4 vid2_d5 video out bit 5 vid2_d6 video out bit 6 vid2_d7 video out bit 7 vid2_field video out field vid2_hsync video out horizontal sync vid2_vsync video out vertical sync table 3-6. video control signal groups video control signal group video signals vc0 vid0_field vid0_vsync vid0_hsync vc2 vid2_field vid2_vsync vid2_hsync
revision 1.1 6/4/12 page 29 confidential max64180 data sheet functional description 3.1.3 video clocks data and control signals are timed against the two vi deo pixel clock signals: video pixel clock 0 and video pixel clock 2. the video pixel clock 0 (vid0_pixclk) is associated with video port 0 and video pixel clock 2 (vid2_pixclk) is associated with video port 2. the video pixel clock pins can be configured either as input or output pins. for example, vid0_pixclk drives the image sensor clock as an input. vid2_pixclk drives the external audio device as an output. th e video input processors and video output processor can select any of the video pixel clock inpu ts as the reference for interface timing. the video output clock pin, vid0_outclk drives the video clock. the video output clock is only a clock source, and video interface signals are not timed against this pin. the video output clock is associated with only video port 0. 3.1.4 video i/o power domains the video input signals (vid0_d[7:0]) for video port 0, video control signal 0 (vc0), video pixel clock 0 (vid0_pixclk), and video output clock (vid0_outclk) are all in the vid0 power domain. the video input signals (vid2_d[7:0]) for video port 2, video control signal 2 (vc2), and video pixel clock 2 (vid2_pixclk) are in the vid2 power domain. the video i/o power domains can be either tied to the same voltage on the board or tied to different voltages on the board. if the video i/o powered domain s are tied to different voltages on the board, use the video control signal group asso ciated with that power domain.
revision 1.1 6/4/12 page 30 confidential max64180 data sheet functional description 3.1.5 video input processor (vip) the max64180 comprises two vips: vip0 and vip1. th e vips perform: ? scaling ? cropping (can be used to reduce input prior to up-scaling) ? luma processing ? chroma processing ? horizontal scaling ? motion adaptive deinterlacing ? vertical scaling ? motion adaptive temporal filtering ? pixel processing extracts video statistics to guide compression each vip has a digital video interface (v in) and a video preprocessor (vpp) module. figure 3-4. video input processor the key benefit of max64180 is th e ability to support different resolu tions for displays, such as local previewing and remote hosting. the max64180 accomplis hes this by processing each input independently in the vin and vpp blocks inside each vip. for systems with a single 8-bi t data input, the video input is replicated into two streams. each stream is individu ally cropped, filtered, resized, and stored in memory. for systems with two 8-bit data inputs, each stream is individually processed and stored in memory. each vin receives video input through the video ports, detects correct synchronization, performs cropping, reframes data, and provides separate luma and chroma outputs to the corresponding vip for further processing. vin1 video input mux memory vid0 vid2 vpp1 video input processor 1 vin2 vpp2 video input processor 0
revision 1.1 6/4/12 page 31 confidential max64180 data sheet functional description the vpp receives data from vip, performs spatial and te mporal filtering on the data to reduce video noise. the vpp alters brightness, contrast, and performs ga mma correction on the luma component of the video. it also adjusts the saturation and hue characteristics by processing the chroma component of the video. the input video is resized and stored in memory. the data flow in the vip is shown in figure 3-5 . figure 3-5. video input processing data flow the horizontal and vertical scale modules use an ei ght-tap, eight-phase programmable finite impulse response (fir) filter. the deinterlacer uses a four-field motion adaptive algorithm. cropping, luma, chroma and h- noise processing input video h-scale motion adaptive de-interlacing v-scale motion adaptive temporal processing pixel processing cropped, scaled, de-interlaced, processed video video statistics scaling portion of vip
revision 1.1 6/4/12 page 32 confidential max64180 data sheet functional description 3.1.6 video output processor (vop) the video output processor is a data driven proc ess that occurs at the vop clock rate. the vop performs: ? luma and chroma vertical and horizontal scaling ? luma edge enhancement ? video and graphics mixing ? hardware cursor ? color processing ? video formatting for desired output: rgb or yuv 4:2:2 figure 3-6 shows the data flow during video output scaling. figure 3-6. video output processing data flow vertical scaling uses up to an eight-tap, eight-ph ase programmable fir filter for luma and chroma. the down-sampling ratio is limited by the quality achievab le with two taps and the frequency of the video output clock. there is no limit on the up-sampling ratio other than the frequency limit imposed by the video output clock. selected video from memory (yuv 4:2:0) mixer, color- processor, hw cursor, output formatting selected , scaled, enhanced, mixed, color- processed formatted video scaling portion of vop graphic channels 1 and 2 luma line buffers luma v-scale sync, line buffers luma edge enhancement luma h-scale chroma line buffers chroma v-scale chroma h-scale two graphic channels from memory
revision 1.1 6/4/12 page 33 confidential max64180 data sheet functional description 3.2 audio subsystem the main functional blocks of the audio subsystem include audio input interface and audio output interface. the audio interface signal group comp rises one stereo input and one stereo output. 3.2.1 audio group signals figure 3-7 illustrates the signal paths and timing fo r the audio interface. figure 3-7. audio group signals 3.2.2 audio clocks the max64180 operates at the following sampling frequencies. ? 48, 24, 12khz ? 44.1, 22.05, 11.025khz ? 32, 16, 8khz the signal group has an independent master clock (mcl k) associated with it. the master clock runs at 256 * fs, where fs is the sampling frequency. the mast er clock can be sourced either from an internal pll or an external clock source. audio output interface aud0_bck aud0_odat0 aud0_spdif audio input interface aud0_idat aud0_lrck aud0_mclk audio pll2 audio pll3
revision 1.1 6/4/12 page 34 confidential max64180 data sheet functional description 3.3 encoder subsystem the max64180 codec supports the following hd encoders and decoders: ? h.264 encoder/decoder ? mpeg2 decoder ? jpeg/mjpeg encoder/decoder the h.264 codec, mpeg2 decoder, and jpeg/mjpeg codec are implemented as three independent blocks in the hardware. as a result, the codecs can run in parallel to support real time transcoding from one format to another. the hardware allows the highest processing power at the lowest power consumption to support tools as specified by the h.264 standard. the processing powe r, which encodes or deco des hd resolutions, can also encode or decode multiple reduced resolutions or sd streams. the h.264 codec encodes or decodes up to 1280 pixels per line (horizontally) and 720 lines (vertically). mpeg2 decoder the hd mpeg2 decoder decodes up to a maximum of 1280 pixels per line (horizontally) and 720 lines (vertically). it does not have enc oding capabilities. the mpeg2 decoder in conjunction with h.264 encoder can be used to create a transcoding application. jpeg/mjpeg en coder/decoder the jpeg/mjpeg codec encodes or decodes up to a maximum of 1280 pixels per line (horizontally) and 720 lines (vertically) at 30fps. the codec supports both yuv 4:2:0 and 4:2:2 modes. table 3-7. supported encoding and decoding modes features baseline profile m ain profile high profile field encoding - yes yes macroblock adaptive frame field (mbaff) - yes yes b frames - yes yes context-based adaptive binary arithmetic coding (cabac) - yes yes 8 x 8 transforms - - yes quantization matrix - - yes weighted prediction - yes yes
revision 1.1 6/4/12 page 35 confidential max64180 data sheet functional description 3.4 host interface an external system host cpu controls the max64180 t hrough the host interfac e. the host interface serves as the compressed data in terface providing direct addressab le access to the external ddr2 sdram, bitstream write fifo, registers and all resources on the codec side of the max64180. the address lines h_addr[6:1] address the desired resource. 3.4.1 host interface connections figure 3-8 shows the host interface connections for the max64180. figure 3-8. host interface connections host_dmarq host_ren host_wen host_waitn host_intn host_d[15:0] host_a[6:1] host_cs0n host chip select 0 host read enable host write enable host wait host interrupt host data[15:0] host dma request host address[6:1]
revision 1.1 6/4/12 page 36 confidential max64180 data sheet functional description 3.4.2 host interface signals the signals that comprise the host interface are described in ta b l e 3 - 8 . table 3-8. host interface pin description pin name signal name direction description host_d[15:0] data [15:0] bidirectional 16-bit bidirectional host data bus host_a[6:1] address [6:1] input host address input pins host_cs0n host chip select 0 input active low host chip select. this signal acts as a chip select input and accesses the max64180?s internal registers, external memory, and bitstream read and write fifo registers. host_ren read enable input active low read enable. the external host processor asserts this input to indicate that it wants to read data from an address inside the max64180. host_intn interrupt output active low ho st interrupt request. this signal has an open-collector output and requires a 1kohm pull-up resistor. host_dmarq host dma request output host direct memory access request host_waitn wait output host wait pin. the max64180 asserts this pin to extend the bus cycle until it is able to accept data (during a write cycle) or present data (duri ng a read cycle). this signal has an open-collector output and requires a 1kohm pull- up resistor.
revision 1.1 6/4/12 page 37 confidential max64180 data sheet functional description 3.5 memory interface the max64180 supports a single external ddr2 sdram memory. ddr2 sdram specifications: ? type supported: ddr2 sdram ? clock frequencies: 233mhz or lower ? bus width: 16-bit ? voltage levels ddr2 sdram: 1.8v (supported by ddr parts) ? maximum density: 64mby tes, one 512mbit x 16-bit ddr2 sdram device 3.5.1 ddr2 sdram connections figure 3-9 shows the ddr2 sdram connections for a single 16-bit ddr2 sdram. figure 3-9. ddr2 sdram connections for 512mb 16-bit ddr_a[12:0] ddr_dq[15:0] ddr_ba1 ddr_ba0 ddr_cke ddr_clk0 ddr_clk0n ddr_dqm1 ddr_dqm0 ddr_dqs1 ddr_dqs1n ddr_dqs0 ddr_dqs0n ddr_csn ddr_casn ddr_rasn ddr_wen max64180 ddr2 sdram signals 16-bit sdram a[12:0] dq[15:0] ba1 ba0 cke ck ck udm ldm udqs udqs ldqs ldqs cs cas ras we
revision 1.1 6/4/12 page 38 confidential max64180 data sheet functional description 3.6 serial interfaces the uart, i 2 c compatible two-wire interface, and spi comprise the serial interfaces. 3.6.1 uart interface the max64180 debug uart port consists of the transmit data (txd) and receive data (rxd) signals (see figure 3-10 ). the mme and arm debug ports along with their txd and rxd signals share the uart port. the debug port is useful for debugging the system and should always be connected to a serial terminal. figure 3-10. uart module to interface signal mapping the uart supports one stop bit, 8 data bits, and even parity. the baud rate for the uart can be set to any of the values listed in ta b l e 3 - 1 0 . table 3-9. serial i/o interfaces interface number of internal instances number of interface ports uart 1 arm + 1 mme 1 twi 1 1 spi 1 1 table 3-10. uart baud rate frequencies baud rate baud rate baud rate baud rate 300 19200 64000 250000 600 28800 76800 256000 1200 38400 115200 460800 2400 51200 128000 500000 4800 56000 153600 576000 9600 57600 230400 921600 mme_dbg_uart arm_dbg_uart txd rxd txd rxd uartd_rxd uartd_txd
revision 1.1 6/4/12 page 39 confidential max64180 data sheet functional description 3.6.2 two-wire (twi) interface the i 2 c compatible two-wire interface comprises one twi module and one twi interface port as shown in figure 3-11 . figure 3-11. twi module to interface signal mapping 3.6.3 spi interface the spi interface comprises two spi modules with one spi port: ? spi_0 (master) is configured to support two devi ces; therefore, it has two slave select (mss) signals. it connects to the primary spi port. ? spi_2 (slave) is configured to support one device; therefore, it has a single slave select (mss) signal. it connects to the primary spi port. spi_0 and spi_2 can be multiplexed because spi_0 is the master and spi_2 is the slave. after reset, this interface comes up in gpio mode, so all signals are inputs. figure 3-12. spi module to interface signal mapping twi_0 twi0_scl scl_0 sda_0 twi0_sda rx spi_mclk spi_2 (slave) spi_mss0 spi_mosi spi_0 (master) tx rx ss0 clk ss1 ss0 clk tx spi_miso spi_mss1 master or slave
revision 1.1 6/4/12 page 40 confidential max64180 data sheet functional description 3.6.4 pulse width modulators the max64180 supports one pwm module. the clock for the module is 1mhz. for programming the pwm pulse width, contact maxim technical support. 3.6.4.1 serial i/o pad programmable features for programming the following features in the max64180, contact maxim technical support. ? drive strength ? slew rate ? pull-up ? pull-down the drive strength groups in max64180 are categorized as follows: ? drive strength 0 (ds0): uart, i 2 c, gpio, pwm ? drive strength 1 (ds1): spi ? drive strength 4 (ds4): video port 0 ? drive strength 6 (ds6): video port 2 ? drive strength 8 (ds8): host ? drive strength 10(ds10): audio a three-bit encoding is used for the actual drive strength value.
revision 1.1 6/4/12 page 41 confidential max64180 data sheet functional description 3.7 usb 2.0 high-speed interface the max64180 contains a high-speed usb 2.0 interface with the ability to operate as a device or host at speeds of up to 480mbps. the usb 2.0 transceiver ma crocell interface (utmi) is an interface between the usb controller and the phy inside the chip. figure 3-13 shows a high-level block diagram of the usb interface. figure 3-13. usb interface block diagram usb 2.0 xo xi vbus dm dp id usb_ana_tst usb connector rext usb d- signal usb d+ signal 3. 4 k ? 1% 100 ?
revision 1.1 6/4/12 page 42 confidential max64180 data sheet functional description 3.7.1 physical layer (phy) the usb 2.0 phy port provides three distinct external interfaces: ? the usb data plus (d+) and data minus (d?) lines: these lines are usb 1.1 and 2.0 specification-compliant. the usb 2.0 phy suppor ts high-speed, 480mbps transfers, as well as usb 1.1 full-speed and low-speed transfers. ? usb 2.0 transceiver macrocell interface (utmi): the usb phy supports the following modes through the utmi: ? high-speed (hs) ? full-speed (fs) ? full-speed-only (fs-only) ? full-speed power-sa ve (fs power-save) ? low-speed power-sa ve (ls power-save) ? low-speed preamble (ls preamble) ? low-speed preamble power-save (ls preamble power-save) ? the utmi contains a receive port, a transmit port, and associated control lines to interface with a usb host controller or device controller. the rece ive and transmit ports can be configured as 8/16-bit parallel ports for all modes of operation. ? serial interface: this interfac e supports full-speed (fs-serial mode) and low-speed (ls-serial mode) data transmission rates to and from a controller. the usb 2.0 phy handles low-level usb protocol and signaling. the usb 2.0 phy supports sync detection, data serialization and deserialization, and data recovery. features the usb 2.0 phy supports the following features. general features ? low power dissipation while active, idle, or on standby ? integrates high-, full-, and low-speed (host mode only) termination and signal switching ? requires minimal external components: a single resistor and single crystal with two capacitors for best operation ? provides an on-chip pll to reduce clock noise and eliminate the need for an external clock generator ? integrates short-to-5-v and short-to-ground protection for d+ and d? lines (requires only global electrostatic discharge (esd) and 5v-compliant dp/dm pads)
revision 1.1 6/4/12 page 43 confidential max64180 data sheet functional description usb 2.0 features ? complies with universal serial bus specification , revision 2.0 ? complies with utmi+ specification , revision 1.0 (level 3) ? integrates 45ohm termination, 1.5kohm pull-up and 15kohm pull-down resistors, with support for independent control of the pull-down resistors ? supports 480mbps high-speed (hs), 12mbps full-speed (fs), and 1.5mbps low-speed (ls) (host mode only) data transmission rates ? supports 8/16-bit unidirectional parallel interfaces for hs, fs, and ls (host mode only) modes of operation, in accordance with the utmi specification ? provides dual (hs/fs) mode host/device sup port (ls operation is not supported for device applications) ? implements data recovery from serial data on the usb connector ? implements sync/end-of-packet (eop) generation and checking ? implements bit stuffing and unstuffing, and bit-stuffing error detection ? implements non return to zero invert (nrzi) encoding and decoding ? implements bit serialization and deserialization ? implements holding registers for staging transmit and receive data ? implements logic to support suspend, resume, and remote wakeup operations ? implements vbus pulsing and discharge se ssion request protocol (srp) circuit ? implements vbus threshold comparators
revision 1.1 6/4/12 page 44 confidential max64180 data sheet functional description 3.7.2 usb controller the usb controller is a dual-role device (drd) controller that supports both device and host functions. it can be configured as a host-only or device-only controller, fully compliant with the usb 2.0 specification . the usb 2.0 configurations support high-speed (hs, 480mbps), full-speed (fs, 12mbps), and low-speed (ls, 1.5mbps) transfers. addition ally, the usb controller can be configured as a usb 1.1 full-speed/low- speed drd. the usb controller is optimized for th e following applications and systems: ? portable electronic devices ? point-to-point applications (no hub, di rect connection to hs, fs, or ls device) ? multi-point applications (as an embedded u sb host) to devices (hub and split support) figure 3-14 shows a block diagram of the usb controller. figure 3-14. usb controller packer fifo controller master bus interface unit slave bus interface unit phy interface unit utmi serial wakeup and power controller media access controller application interface unit dma scheduler receive fifo periodic transmit fifo non-periodic transmit fifo token request uni t token response uni t control and status registers interrupt
revision 1.1 6/4/12 page 45 confidential max64180 data sheet functional description general features ? includes usb power management features ? includes clock gating to save power ? supports packet-based, dynamic fifo memory allocation for endpoints for small fifos and flexible, efficient use of ram ? supports the keep-alive in low-speed mode and start-of-frames (sofs) in high/full-speed modes ? power-optimized design usb 2.0 supported features ? operates in high-speed (hs, 480mbps), full-spe ed (fs, 12mbps) and low-speed (ls, 1.5mbps) modes ? supports session request protocol (srp) ? supports host negotiation protocol (hnp) ?i 2 c interface ? supports a generic root hub ? includes automatic ping capabilities power optimization features ? phy clock gating support during usb suspend mode and session-off mode ? partial power-off during usb suspend mode and session-off mode ? input signals to powered-off blocks driven to safe 0 ? data fifo ram chip-select deasserted when not active ? data fifo ram clock-gating support host architecture the host uses one transmit fifo for all non-periodic out transactions and one transmit fifo for all periodic out transactions. the transm it fifos operate as transmit buffers to hold data (payload of the transmit packet) to be transmi tted over usb. the host pipes the usb transactions through request queues (one for periodic and one for non-periodic). each entry in the request queue holds the in or out channel number along with the information to perform a transaction on the usb. the order in which the requests are written into the queue determines th e sequence of transactions on the usb. the host processes the periodic request queue first, followed by the non-periodic request queue at the beginning of each (micro) frame.
revision 1.1 6/4/12 page 46 confidential max64180 data sheet functional description the host uses one receive fifo for all periodic and no n-periodic transactions. the fifo acts as a receive buffer to hold received data (payload of the received packet) from the usb until it is transferred to the system memory. the status of each packet received also goes into the fifo. the status entry holds the in channel number along with other information, such as received byte count and validity status, to perform a transaction on the amba high-speed bus (ahb). device architecture the device uses a single transmit fifo to store data for all non-periodic endpoints, and one transmit fifo per periodic endpoint to store data to be transmitted in the next (micro) frame. the data is fetched by the dma engine or is written by the application into the transmit fifos and is transm itted on the usb when the in token is received. the request queue contains the number of endpoints for which the data is written into the data fifo. to improve performance, the application can use the l earning queue to help predict the order in which the usb host will access the non-periodic endpoints an d writes the data into the non-periodic fifo accordingly. since each periodic in endpoint has its own fifo, no order prediction is needed for periodic in transfers. the device uses a single receive fifo to receive the data and status for all out endpoints. the status of the packet includes the size of the received out data packet, data parameter identification data (pid), and validity of the received data. the data in the rece ive fifo is read by the dma or the application when the data is received.
revision 1.1 6/4/12 page 47 confidential max64180 data sheet functional description 3.8 high-speed bitstream the bitstream port provides a bidirectional serial data port for input and output of compressed bitstreams with an associated valid signal. the bitstream interfac e streams high-speed bitstream data directly to and from the max64180 codec or soc mode at 30 to 74.5mhz. the bitstream interface multiplexes with the serial peripheral interface (spi) signals. note: the maximum frequency when running with the internal clo ck is 67.5mhz. this is due to a limitation in the granularity (step size) of the pll. figure 3-15. high-speed bitstream signals bs_clk source bs_clk clock and enable control bs_en bs_data bs_req bsdatadir serial data in serial data out de-serializer serializer
revision 1.1 6/4/12 page 48 confidential max64180 data sheet functional description 3.8.1 bitstream signals 3.8.2 bitstream mode in bitstream mode, all signals are active high or active rising edge. bs_clk and bs_en can be programmed to be active falling edge or active low. ?clock plus enable mode? on page 49 explains the primary way in which the control signals are used. table 3-11. bitstream signals signal direction description transmitter receiver bs_clk input or output output or input bitstream clock. data gets latched by this signal. it can be provided either by the max64180 or externally. the bitstream interface supports data transfers up to 74mhz. bs_data output input bitstream data bs_en output input bitstream enable. this signal can be used to qualify bs_clk. bs_en is always in the same direction to bs_data. bs_req input output bitstream request. a request signal used for flow control. bs_req is always in the opposite direction to bs_data.
revision 1.1 6/4/12 page 49 confidential max64180 data sheet functional description 3.8.3 clock plus enable mode the clock plus enable mode is bs_clk enabled, wh ich is qualified by bs_en. when bs_en is active and a bs_clk edge event occurs, the data on bs_data is latched. figure 3-16. receive with bitstream clock and bitstream enable timing some points to note about the waveform figure are given below: ? cycle 1: the receiver is not ready for data, so bs_req is not asserted. ? cycle 2 and 3: the receiver is ready since bs_re q is asserted. the transmitter is not yet sending data because bs_en is not asserted. ? cycle 4-6: both the transmitter and receiver are ready and data is being transferred. ? cycle 7: the receiver has de-asserted bs_req indicating it cannot receive any more data. however, it is necessary that the receiver be designed to accept all bits in the current byte being transferred. when the max64180 is in transmit mode, it can stop transfers only at byte boundaries. in receive mode, the max64180 expec ts the transmitter to stop only at a byte boundary. ? cycle 8: the clock does not need to be free-running.
revision 1.1 6/4/12 page 50 confidential max64180 data sheet functional description 3.9 reset logic the reset block resets the core logic along with the peripheral blocks that surround it. the core reset signal consists of the po wer-on reset signal from an ex ternal pin (resetn), a watchdog reset, and software controlled chip reset signal. 3.9.1 power-on reset the power-on reset signal comes directly from th e external resetn pin and is asynchronous with respect to the clock. it is assumed that the clock is not running both at the time of assertion and deassertion of the power-on reset signal. 3.9.2 watchdog reset the watchdog reset is asserted when the internal watchdog logic detects an internal error. the watchdog reset needs to be enabled before it can take effe ct. resetting the watchdog timer will cause the watchdog reset to be de-asserted, so it is self-clearing. 3.9.3 software chip reset the software chip reset is ored with the watchdog reset. resetting the software chip reset register causes the software chip re set signal to be deasserted, so it provides a form of self-clearing mechanism. all three of these resets get combined into a signal th at resets both the core and the peripheral blocks that surround it. in addition, the reset registers allow ea ch of the peripheral blocks to be reset independently. since control of these reset signals is done using so ftware apis, they are not discussed in this manual.
revision 1.1 6/4/12 page 51 confidential max64180 data sheet functional description 3.9.4 reset timing figure 3-17 shows the timing for the active low reset sig nal resetn. this signal must remain low for a minimum of 300second after the powe r supplies and input clocks stabilize. figure 3-17. reset timing 1.05v core power supply 0v (ground level ) 0v (ground level ) 1/8 / 3.3v t lag 1t on t lag 2 t off 1.8 / 3.3v i/o power supply 1.05v t reset resetn
revision 1.1 6/4/12 page 52 confidential max64180 data sheet functional description 3.10 clocks and phase lock loops (plls) the max64180 internally creates mu ltiple clocks to minimize po wer consumption and maximize performance. all of the clocks are de rived from a single 12mhz crystal os cillator that is bu ilt into the usb interface block. the oscillator can be used even when the usb interface is not used. 3.10.1 clock and pll inputs the max64180 can source the system clock from a 12mhz crystal or a 27 mhz oscillator. the oscillator is used in systems that require the video input to be synchronized to a clock source. for systems that need usb functionality and video synchronized to a clock so urce, both the crystal and oscillator are required. in such a case, the 12mhz crys tal generates the clock to the usb cont roller and the input from the oscillator will be used to generate the clocks to the rest of the system. refer ?crystal and external clock connected to external clk_in pin? on page 57 . the clk_sel pin shown in figure 3-18 selects the clock source for system clock generation. figure 3-18. clocking structure divider divider divider core clocks (multiple) oscillator 2 pll 1 pll 0 scaler sdram clocks arm clock scaler 2 ahb clock 4 apb clock divider uart clock divider timer clock divider spi clock divider bitstream clock divider twi clock pll scaler usb clock usb_xi usb_xo clk_in clk_sel audio and video clock logic vid0_pixclk vid2_pixclk aud0_mclk to vin 0 to vin 1 540 mhz to vout to aoi and aii to internal logic vid0_outclk
revision 1.1 6/4/12 page 53 confidential max64180 data sheet functional description 3.10.2 phase lock loops a total of five plls exist in the ma x64180. one pll is included as part of usb phy, which is used for usb phy clocking and utmi interfacing to the internal us b mac. the remaining four plls generate the other required clock frequencies. pll1 generates the fo ur-phase sdram clocking. pll0 generates the codec core clocks, arm processor, host bus clocks, and i nput clocks for pll2 and pll3. audio and video clocks can be generated from either pll2 or pll3, depen ding on the configuration of the multiplexers. the remainder of the clocks are used for peripheral i/o circuitry and are discussed in their individual sections. 3.10.3 video and audio clocks figure 3-19 shows the circuitry which generates the video in put, video output, and audio clocks. each is discussed in the sections that follow. figure 3-19. video and audio clocks divider pll 2 vid0_pixclk oe vid2_pixclk oe clkinv clkinv clkinv to vin (0) to vin (1) to vout oe vid0_outclk aud0_mclk oe pll 3 540 mhz from scaler to audio interface ena ena ena ena to and from internal logic divider divider
revision 1.1 6/4/12 page 54 confidential max64180 data sheet functional description 3.10.3.1 video input clocks the two video input interfaces vin0 and vin1 prov ide the video pixel clock signals: vid0_pixclk and vid2_pixclk. the video pixel clock signals are the syn chronization clocks for video data. alternately, an inverted version of the video pixel clock can be used to time the interface. the video pixel clock pad can be configured to be either an input or output. in input mode, the pixel clock is driven from an exte rnal source. in output mode, the pixel clock is driven from an internal clock generator, and the clock is routed to drive both the internal logic and external devices through the i/o cell. in other words, the clo ck supplied to the video input circuitry is always the signal from the i/o pad regardless of whether th e video pixel clock is in input or output mode. 3.10.3.2 video output clocks the max64180 also has the capabilit y to generate the vide o output clock source , vid0_outclk. this mode is useful in interfacing to sensors that requ ire a clock input and send a clock output (which is typically a recovered, delayed version of the input clock) with the data. the internal video out (vout) signal (see figure 3-19 ) that goes to the internal video output circuitry can only be sourced by vid2_pixclk. alternately, an inverted version of vid2_pixclk can be used to time the interface. the vid2_pixclk pad can be either an output or inpu t. in output mode, vid2_pixclk is driven from the internal clock generators. in input mode, vid2 _pixclk is driven from an external source. 3.10.3.3 audio clocks when the bidirectional audio master clock pin, aud0_mclk, is configured as an input, it provides the clock for the internal audio input interface and audi o output interface blocks. in output mode, the audio clock is driven from internal clock generators, and the clock is routed to drive the logic through the i/o cell. pll0 generates the main clock from which all other clocks in the system are derived.
revision 1.1 6/4/12 page 55 confidential max64180 data sheet functional description 3.11 device configuration the section below describes how the device can be configured. 3.11.1 reset when the device is first powered on, the power supplies must be brought up in the order shown in ?power supply sequencing? on page 59 . when the power supplies become stable, follow this procedure to reset the max64180. to reset the max64180 to master (soc) mode: 1. set clk_sel pin to select the source clock fo r the plls. the clock can come from either the internal usb oscillator or the clk_in pin. 2. set the host_cfg_0 pin to 1 to select master configuration mode . 3. set the boot mode using (cfg) pin. see table 3-12 for more information. 4. assert the resetn pin low for at leas t one microsecond and then release it. at this point, the boot rom in the ch ip will start the initialization process. to reset the max64180 to slave (coprocessor) mode: 1. set clk_sel pin to select the source clock fo r the plls. the clock can come from either the internal usb oscillator or the clk_in pin. 2. set the host_cfg_0 pin to 0 to select parallel slave configuration mode . 3. set the boot mode using cfg pin. see table 3-12 for more information. 4. assert the resetn pin low for at leas t one microsecond and then release it. at this point, the video multi-media engine (mme) is ready to accept the downloaded firmware image. configure the configuration/status registers, download the firmware, a nd start the other clocks. wait for the max64180 to return a valid gpb (global pointer block). 3.11.2 boot mode for the mmes and the arm at power-on, an on-chip rom that contains the b ootrom code executes the code and checks the clock source (clk_sel) and boot mode (cfg). the bootro m code then copies the boot loader from the specified boot device. table 3-12. boot modes configuration (cfg) boot mode 0 load from spi eeprom (spi 0) 1 load from uart debug using xmodem
revision 1.1 6/4/12 page 56 confidential max64180 data sheet functional description 3.11.3 api configuration the apis initialize the internal registers as part of the configuration process. the registers include: ? configuration and control registers ? drive strength, slew rate control registers ? clock and pll registers the default configuration for the clock and pll regi sters assumes that the 12mhz usb crystal is being used as the primary clock source. an externally generated 24 or 27mhz clock can also be used to drive the max64180. if an external clock is being used, contact maxim technical support for a specialized version of the api. 3.11.4 pin muxing all shared i/o pins come up in the primary interface mode, and they must be programmed to be used in the alternate interface mode or gpio mode. dedicated gp io pins come up as input pins and must be programmed to be used as output pins. 3.11.5 debug mode the api supports communication between the arm pr ocessor and the debug po rt. the debug port is useful in debugging the system and should al ways be connected to a serial terminal. 3.12 oscillator connections the usb 2.0 phy supports the following reference clock sources. 3.12.1 crystal connected to usb_xin and usb_xo pins figure 3-20 shows the clock configuration with an external crystal. figure 3-20. clock configuration with an external crystal usb_xin usb_xo clk_in clk_sel 12mhz crystal 0 0
revision 1.1 6/4/12 page 57 confidential max64180 data sheet functional description the crystal must have a fundamental frequency of 12mhz and must meet the specifications shown in ta b l e 3 - 1 3 . 3.12.2 crystal and extern al clock connected to external clk_in pin figure 3-21 shows the clock configuration when the external clk_in pin is used. in this mode, both the external crystal and the external clk_in pin are connected. figure 3-21. clock configuration with an external crystal the crystal must have a fundamental frequency of 12mhz and meet the specifications shown in ta b l e 3 - 1 3 . the external clock must have a fundamental frequency of 24 or 27mhz with a frequency tolerance of 200ppm, a peak jitter of 100ps., a duty cycle between 40/60 and 60/40, and a signal swing equal to the host power supply voltage. table 3-13. crystal specifications parameter value frequency tolerance 200ppm peak jitter 100ps output differential voltage > 500mv w.r.t xi shunt capacitance 5 ? 8pf load capacitance 15-30pf series resistance 20-60ohms drive level 50-500w external 24/27mhz clock usb_xin usb_xo clk_in clk_sel 12mhz crystal 1
revision 1.1 6/4/12 page 58 confidential max64180 data sheet functional description figure 3-22 shows the clock configuration where the crystal clock is not connected in the design, but only the external clock is connected to clk_in. figure 3-22. clock configuration with an external crystal in this mode, the usb will not be operational because the usb runs on ly when using the crystal. this configuration is typically used in coprocessor applications. the external clock must have a fundamental frequency of 24 or 27mhz with a frequency tolerance of 200 ppm, a peak jitter of 100ps., a duty cycle between 40 /60 and 60/40, and a signal swing equal to the host power supply voltage. external 24/27mhz clock usb_xin usb_xo clk_in clk_sel 1
max64180 data sheet power supply considerations revision 1.1 6/4/12 page 59 confidential 4 power supply considerations this section provides detailed information concerning the power supply considerations of the max64180 to help ensure first time success in implementing a functional design, which has been optimized for signal quality. 4.1 power supply sequencing figure 4-23 provides the recommended power-up and power- down sequences. in an ideal design, all of the power supplies become stable at the same time to prevent any direct feed-through current. in real designs, however, there is typically a time delay before the power supplie s stabilize. this section describes the restrictions on the time differences between the power supplies. figure 4-23. power supply sequencing the max64180 uses three different power rails: 1.5v fo r the core, 1.8v for ddr i/os, and 3.3v for all other i/os. when the 1.5v core supply becomes stable, the 1.8v and 3.3v i/o voltages can be brought up at any time and in any order. during power-down, the i/o voltages must be brought down before the core voltage. the t reset has to be greater than 1 micro second. the restrictions are listed below: t lag 1, t lag 2 >= 0 ms. t on , t off >= 0 ms. 1.05v core power supply 0v (ground level ) 0v (ground level ) 1/8 / 3.3v t lag 1t on t lag 2 t off 1.8 / 3.3v i/o power supply 1.05v t reset resetn
max64180 data sheet power supply considerations revision 1.1 6/4/12 page 60 confidential 4.2 power supply the current requirements are different for each powe r domain and are dependent on the target application. table 4-14 shows the peak current requirements for each domain. the peak current is used for regulator and decoupling capacitors sizing. it does not represent typical power consumption. maximum power consumption for the supp orted application is less than 1.5w. table 4-14. peak power supply currents for the different power domains interface power domain conditions peak units core core_vdd 1.0 volt supply voltage 1000 ma audio aud_vdd 3.3 volt supply voltage 25 ma host host_vdd 3.3 volt supply voltage 60 ma ddr2 sdram memory ddr_vdd 1.8 volt supply voltage (vdda) 250 ma usb usb_vdd 3.3 volt supply voltage 60 ma video vid0_vdd 3.3 volt supply voltage 25 ma vid2_vdd 3.3 volt supply voltage 65 ma
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 61 confidential 5 electrical specifications this section provides the absolute maximum rating s, stress ratings, recomme nded operating conditions, dc characteristics, and ac char acteristics for the max64180. 5.1 operating parameters absolute maximum ratings supply voltage range on core_vdd .............................................................................................. .............................................. 1.5v supply voltage range on ddr_vdd ............................................................................................... ............................................... 2.5v supply voltage range on vid0_vdd and vid2_vdd .................................................................................. ................................... 4.5v supply voltage range on aud_vdd ............................................................................................... ............................................... 4.5v supply voltage range on host_vdd .............................................................................................. .............................................. 4.5v supply voltage range on usb_vdd ............................................................................................... ................................................ 4.5v maximum input voltage (vref) ................................................................................................. ............................vdd_vref+700mv maximum input voltage, ddr........................................................................................................................... ddr_vdd+300mv 2.1v storage temperature range ...................................................................................................... ..................................... ?40c to 150c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 5-15. recommended dc operating conditions interface signal name min typ max units description core core_vdd pll_vdd 1.0 1.05 1.10 v 1.05v 5% video vid0_vdd vid2_vdd 1.71 1.8 1.89 v 5% 2.37 2.5 2.62 3.13 3.3 3.46 audio aud_vdd 1.71 1.8 1.89 5% 2.37 2.5 2.62 v 3.13 3.3 3.46 host host_vdd 3.13 3.3 3.46 v 3.3v 5% usb usb_vdd 2.97 3.3 3.63 v 3.3v 10% usb_vbus 1 1. the vbus pin can sink or source 8ma of current. therefore, to meet the design specification, the external power supply must b e able to source at least 10ma at a voltage level of 5v 4%. t he vbus pin presents a worst-case load of 500ff. this worst-case load is for the usb 2.0 phy only and does not account for capacitance due to routing, pads, package, or board traces. 4.855.2v5v 4% memory ddr_vdd 1.7 1.8 1.9 v 1.8v 0.1v ddr_vref - 0.60 x ddr_vdd - v this should be tuned for every design. refer to the ddr design guideline, " mg3500/mg2580 ddr2 user's guide .? use 1% resistors operating temperature range 0 - 70 c ambient temperature
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 62 confidential 5.2 dc characteristics table 5-16 defines the dc characteristics for all interfaces except the ddr2 sdram interface. table 5-17 defines the dc and ac characte ristics for ddr2 sdram interface. table 5-16. dc characteristics symbol parameter conditions vid0_vdd, vid2_vdd, aud_vdd, 3.3v 5% vid0_vdd, vid2_vdd, aud_vdd, 2.5v 5% vid0_vdd, vid2_vdd, aud_vdd, 1.8 v 5% units min max min max min max v ih input high-level voltage v dd = maximum 2.00 ? 1.6 ? 1.3 ? v v il input low-level voltage v dd = minimum ? 0.4 ?0.4 ?0.4 v v oh output high-level voltage v dd = minimum, i oh = ?4ma 2.70 ? 1.9 ? 1.4 ? v v ol output low-level voltage v dd = minimum, i ol = ?4ma ? 0.35 ? 0.35 ? 0.35 v i ih input high-level leakage v dd = maximum, v in = v dd ?5 +5 ?5 +5 ?5 +5 a i il input low-level leakage v dd = maximum, v in = 0v ?5 +5 ?5 +5 ?5 +5 a c pin capacitance ? ? 5 ? 5 ? 5 pf table 5-17. dc and ac characteristics for ddr2 sdram symbol parameter conditions ddr_vdd 1.8 v 100mv units min max v dcih input dc high-level voltage v dd = maximum ddr_vref +125mv ddr_vdd +300mv v v dcil input dc low-level voltage v dd = minimum 0 ddr_vref ?125mv v v acih input ac high-level voltage v dd = maximum ddr_vref +250mv ddr_vdd +300mv v v acil input ac low-level voltage v dd = minimum 0 ddr_vref ?250mv v v dcoh output dc high-level voltage v dd = maximum 1.4 ddr_vdd v v dcol output dc low-level voltage v dd = minimum 0 ddr_vref ? 250mv v v acoh output ac high-level voltage v dd = maximum 1.3 ddr_vdd v v acol output ac low-level voltage v dd = minimum 0 0.5 v c pin capacitance ? ? 5 pf
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 63 confidential 5.3 ac timing this section provides the ac timing for the max64180?s various interfaces. this section is divided into the following subsections: ? ?video interface ac timing? on page 64 ? ?audio interface ac timing? on page 66 ? ?host interface ac timing? on page 68 ? ?spi/bitstream interface ac timing? on page 72
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 64 confidential 5.3.1 video interface ac timing figure 5-24. video interface timing table 5-18. standard definition video interface timing parameters signal parameter description timing value (ns) 1 1. all timing values are with respect to the rising edge on the vid_pixclk pin. this clock can be supplied either by an external device or by the max64180. min typ max vid[0,2]_pixclk t vc video pixel clock cycle time (27mhz) ? 37.037 t vh video pixel clock high time 16.67 18.5 20.37 t vl video pixel clock low time t vc - t vh t vr video pixel clock slew (r ise time) not applicable t vf video pixel clock slew (f all time) not applicable vid0_d[7:0], hsync[0], vsync[0], field[0] t vis video data, horizontal sync , vertical sync, field setup time to video pixel clock 0 3.5 ? ? t vih video data, horizontal sync , vertical sync, field hold time from video pixel clock 0 2.8 ? ? vid2_d[7:0], hsync[2], vsync[2], field[2] t vis video data, horizontal sync , vertical sync, field setup time to video pixel clock 2 3.5 ? ? t vih video data, horizontal sync , vertical sync, field hold time from video pixel clock 2 2.8 ? ? vid[2]_d[7:0], hsync[2], vsync[2], field[2] *vid2 port is output. t vcq video data, horizontal sync , vertical sync, field delay from video pixel cl ock 2. video pixel clock 2 is configured as output clock. 4.0 ? 13 t vf t vis t vih t vc t vcq t vl t vh t vr t vis vid[0,2]_pixclk vid[0,2]_d[7:0] vid[2]_d[7:0] hsync, vsync, field
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 65 confidential table 5-20. high-speed video interface timing parameters table 5-19. high definition video interface timing parameters signal parameter description timing value (ns) 1 min typ max vid[0,2]_pixclk t vc video pixel clock cycle time (74.25mhz) ? 13.468 t vh video pixel clock high time 6.06 6.73 7.41 t vl video pixel clock low time t vc - t vh t vr video pixel clock slew (r ise time) not applicable t vf video pixel clock slew (fall time) not applicable vid0_d[7:0] 2 , hsync[0], vsync[0], field[0] t vis video data, horizontal sync, vertical sync, field setup time to video pixel clock 0 2.5 ? ? t vih video data, horizontal sync, vertical sync, field hold time from video pixel clock 0 2.8 ? ? vid[2]_data 2 , hsync[2], vsync[2], field[2] t vis video data, horizontal sync, vertical sync, field setup time to video pixel clock 2 2.5 ? ? t vih video data, horizontal sync, vertical sync, field hold time from video pixel clock 2 2.8 ? ? 1. all timing values are with respect to the rising edge on the vid_pixclk pin. this clock should be supplied either by an external device or by the max64180. 2. the external device should drive the data on the fa lling edge of vid_pixclk to satisfy the input hold requirements. signal parameter description timing value (ns) 1 1. all timing values are with respect to the rising edge on the vid_pixclk pin. this clock should be supplied either by an external device or by the max64180. min typ max vid[0,2]_pixclk t vc video pixel clock cycle time (100mhz) ? 10 t vh video pixel clock high time 4 5 6 t vl video pixel clock low time t vc - t vh t vr video pixel clock slew (r ise time) not applicable t vf video pixel clock slew (fall time) not applicable vid0_d[7:0] 2 , hsync[0], vsync[0], field[0] 2. the external device should drive the data on the fa lling edge of vid_pixclk to satisfy the input hold requirements. t vis video data, horizontal sync, vertical sync, field setup time to video pixel clock 0 2.5 ? ? t vih video data, horizontal sync, vertical sync, field hold time from video pixel clock 0 2.8 ? ? vid[2]_data 2 , hsync[2], vsync[2], field[2] t vis video data, horizontal sync, vertical sync, field setup time to video pixel clock 2 2.5 ? ? t vih video data, horizontal sync, vertical sync, field hold time from video pixel clock 2 2.8 ? ?
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 66 confidential 5.3.2 audio interface ac timing figure 5-25 shows the i 2 s protocol, where the most significant bit is sent one audio bit clock (aud0_bck) cycle after the audio left right clock (aud0_lrck) signal has transitioned. in this mode, when lrck is high, the data is from the right channel, and when lrck is low, the data is from the left channel. figure 5-25. standard audio timing figure 5-26 shows sample waveforms for 16-bit left-justified audio. the most significant bit for each audio sample is aligned with lrck's transition. the audio input interface ignores the data bus after the least significant bit for each sample. figure 5-26. 16-, 20-bit left justified audio waveform aud0_mclk aud0_lrck aud0_bck 256 audx_mclks 64/32 aud_bcks aud0_idat aud0_odat0 aud0_bck aud0_lrck 16-bit 20-bit msb n n+1 n+15 lsb msb n n +1 n+ 19 n+15 n+31 or n+ 31
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 67 confidential figure 5-27. audio interface timing ta b l e 5 - 2 1 lists the ac timing for audio operations. table 5-21. audio interface timing parameters signal parameter description timing value (ns) min typ max aud0_bck t bc audio bit clock cycle time (fs = 48khz, 64 bck/sample) ? 325.5 ? t bc audio bit clock cycle time (fs = 48khz, 32 bck/sample) ? 651.04 ? t bc audio bit clock cycle time (fs = 32khz, 64 bck/sample) ? 488.28 ? t bc audio bit clock cycle time (fs = 32khz, 32 bck/sample) ? 976.56 ? t bh audio bit clock high time t bc /2 * 0.8 t bc /2 t bc /2 * 1.2 t bl audio bit clock low time (t bc - t bh )t bc ? t bh t br audio bit clock slew (rise time) ? ? 3 t bf audio bit clock slew (fall time) ? ? 3 aud0_lrck aud0_odat0 aud0_idat t dvw 1 1. there is no restriction on the position of the data valid window relative to bck. the internal data sampling position is programmable and can be repositioned in t bc . data valid window for slave mode operation (fs = 48khz or 32khz) t bc /4 + 15 ? ? t dvw data valid window for master mode operation (fs = 48khz or 32khz) t bc /4 ? 15 ? ? aud0_bck aud0_lrck aud0_idat aud0_odat0 t bf t dvw t bc t bl t bh t br t dvw
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 68 confidential 5.3.3 host interface ac timing figure 5-28. host interface timing host_cs0n host_a[6:1] host_d[15:0] host_wen host_ren host_dmarq address address write data read data t was t wdc t wah t wdh t ras t rah t rdd t wec t cwe t wea t csh t rdv t rdh max 4 clk + t rqd host_dmarq takes three to four core clock (clk) periods before becoming valid t csa t cre t rec t rea
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 69 confidential figure 5-29. host direct memory access (dma) timing figure 5-30. host wait timing clk host_wen host_ren host_dmarq t clk t clk represents ddr2 sdram cl ock cycles, not xin cycles host_dmarq takes three to four core clock (clk) periods before becoming valid t rqd clk host_wen host_ren host_waitn host_wen host_ren host_waitn the host interface needs three to four core clock (clk) cycles at the end of a host access before host_waitn is valid. t wd t clk t wv short time between accesses <2 core clock periods t wd t wv long time between accesse s >2 core clock periods the host interface generates host_waitn from the core clock so the leading edge of host_ren or host_wen, host_waitn may not be valid for one core clock (clk) cycle, plus some combinatorial delay. t clk represents internal core clock (clk) cycles, not xin cycles
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 70 confidential figure 5-31. host interrupt timing table 5-22. host interface timing parameters signal parameter description min max units core clock t clk crystal oscillator (xin x pll) frequency ? 180 mhz host_a[6:1] t was host address setup to trailing edge host write enable for write cycles 20 ? ns t wah host address hold from trailing edge host write enable for write cycles 3 ? ns t ras host address setup to leading edge host read enable for read cycles 0 ? ns t rah host address hold from trailing edge host read enable for read cycles 0 ? ns t csa host address setup to leading edge of host chip select 0 ? ns host_d[15:0] t wdc host data setup to trailing edge host write enable for write cycles 12 ? ns t wdh host data hold from trailing edge host write enable for write cycles 3 ? ns t rdd host data driven from leading edge host read enable for read cycles 0 ? ns t rdv host data valid from leading edge host read enable for read cycles ? 17 ns t rdh host data hold from trailing edge host read enable for read cycles 2 11 ns host_wen t cwe host chip select active to host write enable active 0 ? ns t wec host write enable inactive to host chip select inactive 3 ? ns t wea host write enable active time 20 ? ns host_ren t cre host chip select active to read enable active 0 ? ns t rec host read enable inactive to host chip select inactive 0 ? ns t rea host read enable active time 20 ? ns host_cs0n t csh host chip select inactive time between accesses 10 ? ns clk host_intn t clk t id t clk represents internal core clock (clk) cycles, not xin cycles
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 71 confidential host_dmarq t rqd host direct memory access r equest valid from internal clock ? 8 ns host_intn t id host interrupt valid from internal clock host_waitn t wd host wait valid from internal clock ? 8 ns t wv host wait valid from host read enable/host write enable ? 12 ns signal parameter description min max units
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 72 confidential 5.3.4 ddr2 sdram interface ac timing the max64180 adheres to the jedec definition of timing for sdrams. refer to the appropriate specifications when designing the sdram inte rface: jedec standard jesd79-2c ddr2 sdram specification, http://www.jedec.org/download/search/jesd79-2c.pdf 5.3.5 spi/bitstream interface ac timing this section shows the timing for the serial peripheral interface and bits tream interface. the timing for the two interfaces is identical irrespective of the interface being used. timing is shown for the following set of conditions: 1. bs_clk driven from a source external to the max64180 and data mastered by a source external to the max64180. 2. bs_clk driven from a source external to the max64180 and data mastered by the max64180. 3. bs_clk mastered from the max64180 internal source and data mastered by a source external to the max64180. 4. bs_clk mastered from the max64180 internal source and data mastered by the max64180.
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 73 confidential bs_clk driven from a source external to the max64180 and data mastered by a source external to the max64180 figure 5-32. bitstream timing with an exte rnal clock and external data master bs_clk spi_mclk (pin) t cke t esufe bs_en spi_mss0 (pin) t dsure t esure t dsufe bs_data spi_mosi (pin) t rdvre bs_req spi_mss1 (pin) bs_req spi_mss1 (pin) t rdvfe t eihre t eihfe t dihre t dihfe t rohre t rohfe
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 74 confidential table 5-23. bitstream timing parameters 1 signal parameter description timing value (ns) min typ max bs_clk spi_mclk t cke external clock period 12.0 bs_en spi_mss0 t esufe bitstream enable setup to falling edge of bs_clk 4.0 t esure bitstream enable setup to rising edge of bs_clk 4.0 t eihfe bitstream enable input hold from falling edge of bs_clk 0.5 t eihre bitstream enable input hold from rising edge of bs_clk 0.5 bs_data spi_mosi t dsufe bitstream data setup to falling edge of bs_clk 3.5 t dsure bitstream data setup to rising edge of bs_clk 3.5 t dihfe bitstream data input hold from falling edge of bs_clk 0.5 t dihre bitstream data input hold from rising edge of bs_clk 0.5 bs_req spi_mss1 t rdvfe bitstream request data valid from falling edge of bs_clk 12.5 t rdvre bitstream request data valid from rising edge of bs_clk 12.5 t rohfe bitstream request output hold from falling edge of bs_clk 2.0 t rohre bitstream request output hold from rising edge of bs_clk 2.0
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 75 confidential bs_clk driven from a source external to the max64180 and data mastered by the max64180 figure 5-33. bitstream timing with an external clock and internal data master bs_clk spi_mclk (pin) t cke bs_en spi_mss0 (pin) t edvfe bs_en spi_mss0 (pin) t edvre bs_data spi_mosi (pin) t ddvfe bs_data spi_mosi (pin) t ddvre t rsufe bs_req spi_mss1 (pin) t rsure t eohre t eohfe t dohre t dohfe t rihre t rihfe
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 76 confidential table 5-24. bitstream timing parameters 2 signal parameter description timing value (ns) min typ max bs_clk spi_mclk t cke external clock period 12.0 bs_en spi_mss0 t edvfe bitstream enable data valid from falling edge of bs_clk 12.5 t edvre bitstream enable data valid from rising edge of bs_clk 12.5 t eohfe bitstream enable output hold from falling edge of bs_clk 2.0 t eohre bitstream enable output hold from rising edge of bs_clk 2.0 bs_data spi_mosi t ddvfe bitstream data valid from falling edge of bs_clk 12.0 t ddvre bitstream data valid from rising edge of bs_clk 12.0 t dohfe bitstream data output hold from falling edge of bs_clk 2.0 t dohre bitstream data output hold from rising edge of bs_clk 2.0 bs_req spi_mss1 t rsufe bitstream request setup to falling edge of bs_clk 3.0 t rsure bitstream request setup to from rising edge of bs_clk 3.0 t rihfe bitstream request input hold from falling edge of bs_clk 0.5 t rihre bitstream request input hold from rising edge of bs_clk 0.5
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 77 confidential bs_clk mastered from the max64180 internal source and data mastered by a source external to the max64180 figure 5-34. bitstream timing with an internal clock and external data master bs_clk spi_mclk (pin) t cki t esufi bs_en spi_mss0 (pin) t dsuri t esuri t dsufi bs_data spi_mosi (pin) t rdvri bs_req spi_mss1 (pin) bs_req spi_mss1 (pin) t rdvfi t eihr i t eihf i t dihr i t dihf i t rohr i t rohf i
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 78 confidential table 5-25. bitstream timing parameters 3 signal parameter description timing value (ns) min typ max bs_clk spi_mclk t cki external clock period 14.8 bs_en spi_mss0 t esufi bitstream enable setup to falling edge of bs_clk 2.5 t esuri bitstream enable setup to rising edge of bs_clk 2.5 t eihfi bitstream enable input hold from falling edge of bs_clk 0.5 t eihri bitstream enable input hold from rising edge of bs_clk 0.5 bs_data spi_mosi t dsufi bitstream data setup to falling edge of bs_clk 2.0 t dsuri bitstream data setup to rising edge of bs_clk 2.0 t dihfi bitstream data input hold from falling edge of bs_clk 0.5 t dihri bitstream data input hold from rising edge of bs_clk 0.5 bs_req spi_mss1 t rdvfi bitstream request data valid from falling edge of bs_clk 5.0 t rdvri bitstream request data valid from rising edge of bs_clk 5.0 t rohfi bitstream request output hold from falling edge of bs_clk 2.0 t rohri bitstream request output hold from rising edge of bs_clk 2.0
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 79 confidential bs_clk mastered from the max64180 internal source and data mastered by the max64180 figure 5-35. bitstream timing with an internal clock and internal data master bs_clk spi_mclk (pin) t cki t edvri t rsufi bs_req spi_mss1 (pin) t rsuri bs_en spi_mss0 (pin) bs_en spi_mss0 (pin) t edvfi bs_data spi_mosi (pin) bs_data spi_mosi (pin) t ddvfi t ddvri t eohri t eohfi t dohri t dohfi t rihri t rihfi
max64180 data sheet electrical specifications revision 1.1 6/4/12 page 80 confidential table 5-26. bitstream timing parameters 4 signal parameter description timing value (ns) min typ max bs_clk spi_mclk t cki external clock period 14.8 bs_en spi_mss0 t edvfi bitstream enable data valid from falling edge of bs_clk 5.0 t edvri bitstream enable data valid from rising edge of bs_clk 5.0 t eohfi bitstream enable output hold from falling edge of bs_clk 2.0 t eohri bitstream enable output hold from rising edge of bs_clk 2.0 bs_data spi_mosi t ddvfi bitstream data valid from falling edge of bs_clk 4.5 t ddvri bitstream data valid from rising edge of bs_clk 4.5 t dohfi bitstream data output hold from falling edge of bs_clk 2.0 t dohri bitstream data output hold from rising edge of bs_clk 2.0 bs_req spi_mss1 t rsufi bitstream request setup to falling edge of bs_clk 1.0 t rsuri bitstream request setup to from rising edge of bs_clk 1.0 t rihfi bitstream request input hold from falling edge of bs_clk 0.5 t rihri bitstream request input hold from rising edge of bs_clk 0.5
max64180 data sheet pin definitions revision 1.1 6/4/12 page 81 confidential 6 pin definitions this section contains an illustration of the device pin layout and pin i dentification tables for the max64180. 6.1 max64180 pin configuration?248-pin ctbga the max64180 device is available in a 248-pin , chip scale thin ball grid array (ctbga). figure 6-36 shows the top view of the device. figure 6-36. max64180 soc signal positions (top view) core_ vdd aud_ vdd gnd ddr_ vdd ddr_ clk0n usb_ avdd usb_ dp usb_ gnd gnd 1234567891011 a b c d e f g h j k l 12 13 14 15 16 17 m n p r t u core_ vdd core_ vdd ddr_ vdd ddr_ clk0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd usb_ avdd usb_ avdd ddr_ vdd ddr_ a2 ddr_ a3 ddr_ vdd core_ vdd core_ vdd core_ vdd core_ vdd host_ vdd host_ vdd core_ vdd host_ vdd host_ vdd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd core_ vdd usb_ dvdd gpio _ 02_08 vid2_ pixclk gpio _ 02_06 usb_ gnd usb_ gnd usb_ ana_ tst usb_ gnd usb_ gnd usb_ id usb_ avdd usb_ avdd usb_ rext vid01 _ vdd vid01 _ vdd vid01 _ vdd host_ cfg_0 cfg vid0_ vsync vid0_ field vid0_ hysnc vid0_ d0 vid01 _ vdd core_ vdd aud_ vdd aud0_ odata 0 core_ vdd core_ vdd vid0_ d1 vid0_ d2 vid0_ d4 vid0_ d5 reset n jtag_ tap_ sel aud0_ spdif test aud0_ idat aud0_ lrck core_ vdd aud_ vdd jtag_ tdi core_ vdd core_ vdd ddr_ vdd ddr_ vdd core_ vdd gnd ddr_ dq12 ddr_ padhi ddr_ vdd gnd spi_ miso vid2_ d0 vid2_ d2 vid2_ d4 spi_ mss0 vid2_ hsync vid2_ d3 vid2_ vsync vid2_ d6 vid2_ d1 vid2_ d5 spi_ mss1 spi_ mclk spi_ mosi twi0_ scl vid23 _ vdd host_ d6 host_ d11 host_ d4 host_ d9 host_ d14 host_ d12 gpio_2 uartd _txd host_ waitn host_ d5 host_ d15 host_ d8 host_ d13 gpio_3 uartd _rxd host_ d2 host_ vdd host_ d10 gnd gnd twi0_ sda ddr_ vdd clk_ in clk_ sel host_ a4 pll_ vdd host_ a1 host_ cs0n ddr_ vdd host_ d7 ddr_ vdd host_ a2 host_ intn host_ wen host_ a5 host_ d0 host_ a3 host_ ren host_ d1 host_ a6 host_ dmarq host_ d3 ddr_ a10 ddr_ ba0 ddr_ a1 ddr_ a5 ddr_ ba1 ddr_ a0 ddr_ a8 ddr_ a4 ddr_ a12 ddr_ a7 ddr_ a6 ddr_ a11 ddr_ rasn ddr_ casn ddr_ csn ddr_ cke ddr_ dq0 ddr_ dq4 ddr_ a9 ddr_ dq5 ddr_ dq7 ddr_ wen ddr_ dq10 ddr_ vref0 ddr_ dqs0 ddr_ dq2 ddr_ dq8 ddr_ dqs1 1234567891011121314151617 v aud0_ bck aud0_ mclk jtag_ tck ddr_ dq11 ddr_ padlo ddr_ vdd gnd ddr_ dqm0 ddr_ dq1 ddr_ dqm1 ddr_ dqs0n ddr_ dq3 ddr_ dq15 ddr_ dqs1n a b c d e f g h j k l m n p r t u v usb_ gnd usb_ vbus usb_ dm vid0_ pixclk vid0_ out clk vid0_ d3 vid0_ d6 vid0_ d7 jtag_ trstn jtag_ tdo vid2_ field vid2_ d7 gpio _ 02 _07 18 jtag_ tms 18 ddr_ dq13 ddr_ vref1 ddr_ dq9 ddr_ dq14 ddr_ dq6 gpio_0 gpio_1 pwm_0 ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd vid23 _ vdd usb_ xin usb_ xo gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd core_ vdd gnd gnd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd
max64180 data sheet pin definitions revision 1.1 6/4/12 page 82 confidential figure 6-37. upper-left quadrant gnd 123456789 a b c d e f g h j core_ vdd ddr_ vdd ddr_ a2 ddr_ a3 ddr_ vdd host_ vdd host_ vdd core_ vdd host_ vdd host_ vdd gnd gnd host_ d6 host_ d11 host_ d4 host_ d9 host_ d14 host_ d12 host_ waitn host_ d5 host_ d15 host_ d8 host_ d13 host_ d2 host_ vdd host_ d10 gnd ddr_ vdd clk_ in clk_ sel host_ a4 pll_ vdd host_ a1 host_ cs0n ddr_ vdd host_ d7 ddr_ vdd host_ a2 host_ intn host_ wen host_ a5 host_ d0 host_ a3 host_ ren host_ d1 host_ a6 host_ dmarq host_ d3 gpio_0 gpio_1 pwm_0 gnd gnd gnd gnd gnd gnd gnd gnd gnd core_ vdd core_ vdd aud_ vdd gnd ddr_ vdd ddr_ clk0n usb_ avdd usb_ dp usb_ gnd gnd 1234567891011 a b c d e f g h j k l 12 13 14 15 16 17 m n p r t u core_ vdd core_ vdd ddr_ vdd ddr_ clk0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd usb_ avdd usb_ avdd ddr_ vdd ddr_ a2 ddr_ a3 ddr_ vdd core_ vdd core_v dd core_v dd core_v dd host_ vdd host_ vdd core_ vdd host_ vdd host_ vdd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd core_v dd usb_ dvdd gpio_ 02_08 vid2_ pixclk gpio_ 02_06 usb_ gnd usb_ gnd usb_ ana_ tst usb_ gnd usb_ gnd usb_ id usb_ avdd usb_ avdd usb_ rext vid01_ vdd vid01_ vdd vid01_ vdd host_c fg_0 cfg vid0 _ vsync vid0_ field vid0 _ hysnc vid0_ d0 vid01_ vdd core_ vdd aud_ vdd aud0_ odata0 core_ vdd core_ vdd vid0 _ d1 vid0_ d2 vid0 _ d4 vid0_ d5 resetn jtag_ tap_ sel aud0_s pdif test aud0_ idat aud0_ lrck core_ vdd aud_ vdd jtag_ tdi core_ vdd core_ vdd ddr_ vdd ddr_ vdd core_ vdd gnd ddr_ dq12 ddr_ padhi ddr_ vdd gnd spi_ miso vid2_ d0 vid2 _ d2 vid2_ d4 spi_ mss0 vid2_ hsync vid2_ d3 vid2 _ vsync vid2_ d6 vid2 _ d1 vid2_ d5 spi_ mss1 spi_ mclk spi_ mosi twio_ scl vi d23 _ vdd host_d 6 host_d 11 host_d 4 host_d 9 host_d 14 host_d 12 gpio _2 uartd_ txd host_ waitn host_d 5 host_d 15 host_d 8 host_d 13 gpio _3 uartd_ rxd host_d 2 host_v dd host_d 10 gnd gnd twio_ sda ddr_ vdd clk_ in clk_ sel host_ a4 pll_ vdd host_a 1 host_c s0 n ddr_ vdd host_d 7 ddr_ vdd host_a 2 host_ intn host_ wen host_a 5 host_d 0 host_a 3 host_r en host_d 1 host_a 6 host_ dmarq host_d 3 ddr_ a10 ddr_ ba0 ddr_ a1 ddr_ a5 ddr_ ba1 ddr_ a0 ddr_ a8 ddr_ a4 ddr_ a12 ddr_ a7 ddr_ a6 ddr_ a11 ddr_ rasn ddr_ casn ddr_ csn ddr_ cke ddr_ dq0 ddr_ dq4 ddr_ a9 ddr_ dq5 ddr_ dq7 ddr_ wen ddr_ dq10 ddr_ vref0 ddr_ dqs0 ddr_ dq2 ddr_ dq8 ddr_ dqs1 v aud0_ bck aud0_ mclk jtag_ tck ddr_ dq11 ddr_ padlo ddr_ vdd gnd ddr_ dqm0 ddr_ dq1 ddr_ dqm1 ddr_ dqs0n ddr_ dq3 ddr_ dq15 ddr_ dqs1n a b c d e f g h j k l m n p r t u v usb_ gnd usb_ vbus usb_ dm vid0 _ pixclk vid0 _ out clk vid0 _ d3 vid0 _ d6 vid0 _ d7 jtag_ trstn jtag_ tdo vid2 _ field vid2 _ d7 gpio_ 02_07 jtag_ tms 18 ddr_ dq13 ddr_ vref1 ddr_ dq9 ddr_ dq14 ddr_ dq6 gpio_0 gpio_1 pwm_0 ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd vid23_ vdd usb_ xin usb_ xo gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd core_ vdd gnd gnd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd
max64180 data sheet pin definitions revision 1.1 6/4/12 page 83 confidential figure 6-38. upper-right quadrant core_ vdd aud_ vd d gnd ddr_ vdd ddr_ clk0n usb_ avdd usb_ dp usb_ gnd gnd 1234567891011 a b c d e f g h j k l 12 13 14 15 16 17 m n p r t u core_ vdd core_ vdd ddr_ vdd ddr_ clk0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd usb_ avdd usb_ avdd ddr_ vdd ddr_ a2 ddr_ a3 ddr_ vdd core_ vdd core_ vd d core_ vdd core_ vd d host_ vdd host_ vdd core_ vdd host_ vd d host_ vdd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd core_ vd d usb_ dvdd gpio_ 02_ 08 vid2_ pixclk gpio_ 02_ 06 usb_ gnd usb_ gnd usb_ ana_ tst usb_ gnd usb_ gnd usb_ id usb_ avdd usb_ avdd usb_ rext vid01_ vd d vid01_ vd d vid01_ vd d host_c fg_0 cfg vid0_ vsync vid0_ field vid0_ hysnc vid0_ d0 vid01_ vd d core_ vd d aud_ vd d aud0_ odata 0 core_ vdd core_ vdd vid0_ d1 vid0_ d2 vid0_ d4 vid0_ d5 resetn jtag_ tap_ sel aud0_s pdif test aud0_ idat aud0_ lrck core_ vdd aud_ vd d jtag_ tdi core_ vd d core_ vdd ddr_ vd d ddr_ vdd core_ vd d gnd ddr_ dq12 ddr_ padhi ddr_ vdd gnd spi_ miso vid2_ d0 vid2_ d2 vid2_ d4 spi_ mss0 vid2_ hsync vid2_ d3 vid2_ vsync vid2_ d6 vid2_ d1 vid2_ d5 spi _ mss1 spi_ mclk spi _ mosi twio_ sc l vid23_ vdd host_d 6 host_d 11 host_d 4 host_d 9 host_d 14 host_d 12 gpio_2 uartd_ txd host_ waitn host_d 5 host_d 15 host_d 8 host_d 13 gpio_3 uartd_ rxd host_d 2 host_v dd host_d 10 gnd gnd twio_ sda ddr_ vdd clk_ in clk_ sel host_ a4 pll_ vdd host_a 1 host_c s0n ddr_ vdd host_d 7 ddr_ vdd host_a 2 host_ intn host_ wen host_a 5 host_d 0 host_a 3 host_r en host_d 1 host_a 6 host_ dmarq host_d 3 ddr_ a10 ddr_ ba0 ddr_ a1 ddr_ a5 ddr_ ba1 ddr_ a0 ddr_ a8 ddr_ a4 ddr_ a12 ddr_ a7 ddr_ a6 ddr_ a11 ddr_ rasn ddr_ casn ddr_ csn ddr_ cke ddr_ dq0 ddr_ dq4 ddr_ a9 ddr_ dq5 ddr_ dq7 ddr_ wen ddr_ dq10 ddr_ vref0 ddr_ dqs0 ddr_ dq2 ddr_ dq8 ddr_ dqs1 v aud0_ bck aud0_ mclk jtag_ tck ddr_ dq11 ddr_ padlo ddr_ vdd gnd ddr_ dqm0 ddr_ dq1 ddr_ dqm1 ddr_ dqs0n ddr_ dq3 ddr_ dq15 ddr_ dqs1n a b c d e f g h j k l m n p r t u v usb_ gnd usb_ vbus usb_ dm vid0_ pixclk vid0_ out clk vid0_ d3 vid0_ d6 vid0_ d7 jtag_ trstn jtag_ tdo vid2_ field vid2_ d7 gpio_ 02 _07 jtag_ tms 18 ddr_ dq13 ddr_ vref1 ddr_ dq9 ddr_ dq14 ddr_ dq6 gpio _0 gpio _1 pw m_ 0 ddr_ vdd ddr_ vd d ddr_ vdd ddr_ vd d vid23_ vd d usb_ xin usb_ xo gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd core_ vd d gnd gnd gnd gnd ddr_ vdd ddr_ vd d ddr_ vdd ddr_ vdd usb_ gnd usb_ dp 10 11 12 13 14 15 16 17 gnd gnd gnd gnd usb_ avdd usb_ avdd core_ vdd core_ vdd core_ vdd core_ vdd core_ vdd usb_ dvdd gpio _ 02 _08 vid2_ pixclk gpio _ 02 _06 usb_ gnd usb_ gnd usb_ ana_ tst usb_ gnd usb_ gnd usb_ id usb_ avdd usb_ avdd usb_ rext spi_ miso vid2_ d0 vid2_ d2 vid2_ d4 spi_ mss0 vid2_ hsync vid2_ d3 vid2_ vsync vid2_ d6 vid2_ d1 vid2_ d5 spi_ mss1 spi_ mclk spi_ mosi twi0_ scl vid23 _ vdd gpio_2 uartd _txd gpio_3 uartd _rxd gnd twi0_ sda usb_ gnd usb_ vbus usb_ dm vid2_ field vid2_ d7 gpio _ 02 _07 18 vid23 _ vdd usb_ xin usb_ xo gnd gnd gnd gnd gnd gnd gnd a b c d e f g h j
max64180 data sheet pin definitions revision 1.1 6/4/12 page 84 confidential figure 6-39. bottom-left quadrant ddr_ dq7 core_ vdd aud_ vdd gnd ddr_ vdd ddr_ clk0n usb_ avdd usb_ dp usb_ gnd gnd 1234567891011 a b c d e f g h j k l 12 13 14 15 16 17 m n p r t u core_ vdd core_ vdd ddr_ vdd ddr_ clk0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd usb_ avdd usb_ avdd ddr_ vdd ddr_ a2 ddr_ a3 ddr_ vdd core_ vdd core_v dd core_v dd core_v dd host_ vdd host_ vdd core_ vdd host_ vdd host_ vdd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd core_v dd usb_ dvdd gpio _ 02_08 vid2_ pixclk gpio _ 02_06 usb_ gnd usb_ gnd usb_ ana_ tst usb_ gnd usb_ gnd usb_ id usb_ avdd usb_ avdd usb_ rext vid01 _ vdd vid01 _ vdd vid01 _ vdd host_c fg_0 cfg vid0_ vsync vid0_ field vid0_ hysnc vid0_ d0 vid01 _ vdd core_ vdd aud_ vdd aud0_ odata0 core_ vdd core_ vdd vid0_ d1 vid0_ d2 vid0_ d4 vid0_ d5 resetn jtag_ tap_ sel aud0_s pdif test aud0_ idat aud0_ lrck core_ vdd aud_ vdd jtag_ tdi core_ vdd core_ vdd ddr_ vdd ddr_ vdd core_ vdd gnd ddr_ dq12 ddr_ padhi ddr_ vdd gnd spi_ miso vid2 _ d0 vid2_ d2 vid2_ d4 spi_ mss0 vid2 _ hsync vid2 _ d3 vid2_ vsync vid2_ d6 vid2_ d1 vid2_ d5 spi _ mss1 spi_ mclk spi _ mosi twio_ scl vid23_ vdd host_d 6 host_d 11 host_d 4 host_d 9 host_d 14 host_d 12 gpio_2 uartd_ txd host_ waitn host_d 5 host_d 15 host_d 8 host_d 13 gpio_3 uartd_ rxd host_d 2 host_v dd host_d 10 gnd gnd twio_ sda ddr_ vdd clk_ in clk_ sel host_ a4 pll_ vdd host_a 1 host_c s0 n ddr_ vdd host_d 7 ddr_ vdd host_a 2 host_ intn host_ wen host_a 5 host_d 0 host_a 3 host_r en host_d 1 host_a 6 host_ dmarq host_d 3 ddr_ a10 ddr_ ba0 ddr_ a1 ddr_ a5 ddr_ ba1 ddr_ a0 ddr_ a8 ddr_ a4 ddr_ a12 ddr_ a7 ddr_ a6 ddr_ a11 ddr_ rasn ddr_ casn ddr_ csn ddr_ cke ddr_ dq0 ddr_ dq4 ddr_ a9 ddr_ dq5 ddr_ wen ddr_ dq10 ddr_ vref0 ddr_ dqs0 ddr_ dq2 ddr_ dq8 ddr_ dqs1 1234567891011121314151617 v aud0_ bck aud0_ mclk jtag_ tck ddr_ dq11 ddr_ padlo ddr_ vdd gnd ddr_ dqm0 ddr_ dq1 ddr_ dqm1 ddr_ dqs0n ddr_ dq3 ddr_ dq15 ddr_ dqs1n a b c d e f g h j k l m n p r t u v usb_ gnd usb_ vbus usb_ dm vid0 _ pixclk vid0 _ out clk vid0 _ d3 vid0 _ d6 vid0 _ d7 jtag_ trstn jtag_ tdo vid2 _ field vid2 _ d7 gpio_ 02_07 18 jtag_ tms 18 ddr_ dq13 ddr_ vref1 ddr_ dq9 ddr_ dq14 ddr_ dq6 gpio_0 gpio_1 pwm_0 ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd vid23 _ vdd usb_ xi n usb_ xo gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd core_ vdd gnd gnd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd k l m n p r t u core_ vdd ddr_ vdd ddr_ clk0 gnd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ dq12 ddr_ a10 ddr_ ba0 ddr_ a1 ddr_ a5 ddr_ ba1 ddr_ a0 ddr_ a8 ddr_ a4 ddr_ a12 ddr_ a7 ddr_ a6 ddr_ a11 ddr_ rasn ddr_ casn ddr_ csn ddr_ cke ddr_ dq0 ddr_ dq4 ddr_ a9 ddr_ dq5 ddr_ dq7 ddr_ wen ddr_ dq10 ddr_ vref ddr_ dqs0 ddr_ dq2 ddr_ dq8 ddr_ dqs1 123456789 v ddr_ clk0n ddr_ dq11 ddr_ dqm0 ddr_ dq1 ddr_ dqm1 ddr_ dqs0n ddr_ dq3 ddr_ dq15 ddr_ dqs1n ddr_ dq13 ddr_ vref ddr_ dq9 ddr_ dq14 ddr_ dq6 ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd gnd gnd gnd gnd gnd ddr_ vdd
max64180 data sheet pin definitions revision 1.1 6/4/12 page 85 confidential figure 6-40. bottom-right quadrant core_ vdd aud_ vdd gnd ddr_ vd d ddr_ clk0n usb_ avdd usb_ dp usb_ gnd gnd 1234567891011 a b c d e f g h j k l 12 13 14 15 16 17 m n p r t u core_ vdd core_ vdd ddr_ vdd ddr_ clk0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd usb_ avdd usb_ avdd ddr_ vdd ddr_ a2 ddr_ a3 ddr_ vdd core_ vd d core_v dd core_v dd core_v dd host_ vdd host_ vdd core_ vdd host_ vdd host_ vdd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd core_v dd usb_ dvdd gpio_ 02 _08 vid2_ pixc lk gpio_ 02 _06 usb_ gnd usb_ gnd usb_ ana_ tst usb_ gnd usb_ gnd usb_ id usb_ avdd usb_ avdd usb_ rext vid01_ vdd vid01_ vdd vid01_ vdd host_c fg_0 cfg vid0_ vsync vid0_ field vid0_ hysnc vid0_ d0 vid01_ vdd core_ vdd aud_ vdd aud0_ odata0 core_ vdd core_ vdd vid0_ d1 vid0_ d2 vid0_ d4 vid0_ d5 resetn jtag_ tap_ sel aud0_s pdif test aud0_ idat aud0_ lrck core_ vdd aud_ vdd jtag_ tdi core_ vdd core_ vd d ddr_ vdd ddr_ vd d core_ vdd gnd ddr_ dq12 ddr_ pad hi ddr_ vd d gnd spi_ miso vid2_ d0 vid2_ d2 vid2_ d4 spi_ mss0 vid2_ hsync vid2_ d3 vid2_ vsync vid2_ d6 vid2_ d1 vid2_ d5 spi_ mss1 spi_ mclk spi_ mosi twio_ scl vid23 _ vdd host_d 6 host_d 11 host_d 4 host_d 9 host_d 14 host_d 12 gpio _2 uartd_ txd host_ waitn host_d 5 host_d 15 host_d 8 host_d 13 gpio _3 uartd_ rxd host_d 2 host_v dd host_d 10 gnd gnd twio_ sd a ddr_ vdd clk_ in clk_ sel host_ a4 pll_ vdd host_a 1 host_c s0n ddr_ vdd host_d 7 ddr_ vdd host_a 2 host_ intn host_ wen host_a 5 host_d 0 host_a 3 host_r en host_d 1 host_a 6 host_ dmarq host_d 3 ddr_ a10 ddr_ ba0 ddr_ a1 ddr_ a5 ddr_ ba1 ddr_ a0 ddr_ a8 ddr_ a4 ddr_ a12 ddr_ a7 ddr_ a6 ddr_ a11 ddr_ rasn ddr_ casn ddr_ csn ddr_ cke ddr_ dq0 ddr_ dq4 ddr_ a9 ddr_ dq5 ddr_ dq7 ddr_ wen ddr_ dq10 ddr_ vref0 ddr_ dqs0 ddr_ dq2 ddr_ dq8 ddr_ dqs1 1234567891011121314151617 v aud0_ bck aud0_ mclk jtag_ tck ddr_ dq11 ddr_ padlo ddr_ vd d gnd ddr_ dqm0 ddr_ dq1 ddr_ dqm1 ddr_ dqs0n ddr_ dq3 ddr_ dq15 ddr_ dqs1n a b c d e f g h j k l m n p r t u v usb_ gnd usb_ vbus usb_ dm vid0_ pixclk vid0_ out clk vid0_ d3 vid0_ d6 vid0_ d7 jtag_ trstn jtag_ tdo vid2_ field vid2_ d7 gpio_ 02_07 18 jtag_ tms 18 ddr_ dq13 ddr_ vref1 ddr_ dq9 ddr_ dq14 ddr_ dq6 gpio_0 gpio_1 pw m_0 ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vd d vid23_ vdd usb_ xin usb_ xo gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd core_ vd d gnd gnd gnd gnd ddr_ vd d ddr_ vdd ddr_ vdd ddr_ vd d usb_ avdd gnd gnd gnd gnd gnd vid01 _ vdd vid01 _ vdd vid01 _ vdd host_ cfg_0 cfg vid0_ vsync vid0_ field vid0_ hysnc vid0_ d0 vid01 _ vdd core_ vdd aud_ vdd aud0_ odata 0 core_ vdd core_ vdd vid0_ d1 vid0_ d2 vid0_ d4 vid0_ d5 reset n jtag_ tap_ sel aud0_ spdif test aud0_ idat aud0_ lrck core_ vdd aud_ vdd jtag_ tdi core_ vdd core_ vdd ddr_ vdd ddr_ vdd core_ vdd gnd ddr_ padhi ddr_ vdd gnd 10 11 12 13 14 15 16 17 aud0_ bck aud0_ mclk core_ vdd aud_ vdd jtag_ tck ddr_ padlo ddr_ vdd gnd k l m n p r t u v vid0_ pixclk vid0_ out clk vid0_ d3 vid0_ d6 vid0_ d7 jtag_ trstn jtag_ tdo 18 jtag_ tms gnd gnd gnd gnd gnd gnd ddr_ vdd ddr_ vdd ddr_ vdd ddr_ vdd
max64180 data sheet pin definitions revision 1.1 6/4/12 page 86 confidential 6.2 signal definitions the i/o signal descriptions in the pin i dentification tables use the following terms: ? i?input only ? o?output only ? i/o? input or output ? iod?input/open drain output ?a?analog
max64180 data sheet pin definitions revision 1.1 6/4/12 page 87 confidential 6.3 pin identifications this section contains the functional pin descriptions for the max 64180. the 248 signals are divided into signal groups as shown in ta b l e 6 - 2 7 . table 6-27. signal group names signal group reference audio ?audio signal group,? page 90 video port 0 ?video port 0 signal group,? page 91 video port 2 ?video port 2 signal group,? page 92 host ?host signal group,? page 93 ddr2 sdram ?ddr2 sdram signal group,? page 94 usb ?usb signal group,? page 96 uart ?uart signal group,? page 96 spi ?spi/bitstream signal group,? page 97 twi ?twi signal group,? page 97 pwm ?pwm signal group,? page 98 gpio ?gpio signal group,? page 98 jtag ?jtag signal group,? page 100 configuration ?configuration,? page 100 clock ?clock,? page 101 reset ?reset,? page 101 power and ground ?power and ground pins,? page 102
max64180 data sheet pin definitions revision 1.1 6/4/12 page 88 confidential 6.4 pin muxing many pins are multiplexed which means they can have more than one function. all pins have a primary function, and the name that is assigned to the pin reflects the primary function. many pins have an alternate (alt) function that can be used when their pr imary function is not being used. gpio function is available as an additional third option on few pi ns. gpio pins are available for customer use. table 6-28 shows pins that have multiple functions. signals that are active low end with a lower case ?n?. table 6-28. pin muxing pin primary function alternate function gpio function audio t16 aud0_spdif ? gpio_1_21 video port 0 m16 vid0_hsync ? gpio_2_00 l16 vid0_vsync ? gpio_2_01 l17 vid0_field ? gpio_1_19 video port 1 a18 vid2_field ? gpio_2_09 b15 vid2_hsync ? gpio_2_10 b16 vid2_vsync ? gpio_2_11 host c3 host_intn ? gpio_1_00 configuration k17 cfg ? gpio_2_03 uart b11 uartd_rxd mme_rxd ? a11 uartd_txd mme_txd ? spi/bitstream a14 spi_miso ? gpio_2_16 b14 spi_mss0 bs_en gpio_2_17 a13 spi_mss1 bs_req gpio_2_18 a12 spi_mclk bs_clk gpio_2_19 b13 spi_mosi bs_data gpio_2_20 twi b12 twi0_scl twi1_scl gpio_2_21 c11 twi0_sda twi1_sda gpio_2_22 pwm c9 pwm_0 ? gpio_2_29 gpio
max64180 data sheet pin definitions revision 1.1 6/4/12 page 89 confidential a9 gpio_0 ? gpio_0_00 b9 gpio_1 ? gpio_0_01 a10 gpio_2 ? gpio_0_02 b10 gpio_3 ? gpio_0_03 pin primary function alternate function gpio function
max64180 data sheet pin definitions revision 1.1 6/4/12 page 90 confidential 6.4.1 audio signal group the audio signal group has six signals as shown in ta b l e 6 - 2 9 . the audio group contains one i 2 s input and one i 2 s output that share common clocking. thes e signals are all in the aud power domain. table 6-29. audio signals pin primary function description name type v16 aud0_bck i/o audio port 0 i 2 s bit clock u16 aud0_idat i audio port 0 i 2 s input data u15 aud0_lrck i/o audio port 0 i 2 s left right clock indicates whether data is for the left or right channel v15 aud0_mclk i/o audio port 0 i 2 s master clock (256 ti mes the sampling clock) t15 aud0_odat0 o audio port 0 i 2 s output data t16 aud0_spdif o audio port 0 sony/philips digital interface
max64180 data sheet pin definitions revision 1.1 6/4/12 page 91 confidential 6.4.2 video port 0 signal group video port 0 signal group includes 13 signals to support an 8-bit video input port. these signals are in the vid0 power domain. table 6-30. video port 0 signals pin primary function description name type r18 vid0_d7 i video port 0 data [7:0] p18 vid0_d6 i p17 vid0_d5 i p16 vid0_d4 i n18 vid0_d3 i n17 vid0_d2 i n16 vid0_d1 i m17 vid0_d0 i m16 vid0_hsync i video port 0 horizontal sync l16 vid0_vsync i video port 0 vertical sync l17 vid0_field i video port 0 field m18 vid0_outclk o video port 0 output clock l18 vid0_pixclk i/o video port 0 pixel clock
max64180 data sheet pin definitions revision 1.1 6/4/12 page 92 confidential 6.4.3 video port 2 signal group the video port 2 signal group includes 15 signals to support an 8-bit bidirectional video port. these signals are in the vid2 power domain. table 6-31. video port 2 signals pin primary function description name type b18 vid2_d7 i/o video port 2 data [7:0] b17 vid2_d6 i/o c17 vid2_d5 i/o a17 vid2_d4 i/o c15 vid2_d3 i/o a16 vid2_d2 i/o c16 vid2_d1 i/o a15 vid2_d0 i/o a18 vid2_field i/o video port 2 field b15 vid2_hsync i/o video port 2 horizontal sync d17 vid2_pixclk i/o video port 2 pixel clock b16 vid2_vsync i/o video port 2 vertical sync
max64180 data sheet pin definitions revision 1.1 6/4/12 page 93 confidential 6.4.4 host signal group the host signal group has 28 signals as shown in ta b l e 6 - 3 2 . when the max64180 is in slave mode, the signals allow external processors to access resour ces inside the max64180. the signals are in the host power domain. table 6-32. host signals pin primary function description name type d3 host_a6 i host address bits [6:1] c1 host_a5 i e3 host_a4 i d1 host_a3 i d2 host_a2 i e2 host_a1 i e1 host_cs0n i host chip select b6 host_d15 i/o host data bits [15:0] a7 host_d14 i/o b8 host_d13 i/o a8 host_d12 i/o b4 host_d11 i/o c7 host_d10 i/o a6 host_d9 i/o b7 host_d8 i/o b3 host_d7 i/o a4 host_d6 i/o b5 host_d5 i/o a5 host_d4 i/o a3 host_d3 i/o c5 host_d2 i/o a2 host_d1 i/o b2 host_d0 i/o c2 host_dmarq o host direct memory access request c3 host_intn iod host interrupt. in host slave mode, this signal is an open-collector output and requires a 1kohm pull-up resistor. b1 host_ren i host read enable c4 host_waitn iod host wait. this signal is alwa ys active low. in host slave mode, this signal is an open-collector output and requires a 1kohm pull-up resistor. a1 host_wen i host write enable
max64180 data sheet pin definitions revision 1.1 6/4/12 page 94 confidential 6.4.5 ddr2 sdram signal group the ddr2 sdram signal group has 48 signals as shown in ta b l e 6 - 3 3 . the max64180 supports a single 16-bit ddr2 sdram configuration. thes e signals are in the ddr power domain. table 6-33. ddr2 sdram signals pin primary function description name type u10 ddr_padhi a driver compensation for ddr2 v10 ddr_padlo a driver compensation for ddr2 m3 ddr_a12 o sdram address bits [12:0] n3 ddr_a11 o k3 ddr_a10 o p1 ddr_a9 o m1 ddr_a8 o n1 ddr_a7 o n2 ddr_a6 o l2 ddr_a5 o m2 ddr_a4 o j1 ddr_a3 o j2 ddr_a2 o k1 ddr_a1 o k2 ddr_a0 o l3 ddr_ba0 o bank address bit [0] l1 ddr_ba1 o bank address bit [1] p3 ddr_casn o column access strobe r2 ddr_cke o clock enable u9 ddr_clk0 o primary clock v9 ddr_clk0n o primary clock complement r1 ddr_csn o chip select
max64180 data sheet pin definitions revision 1.1 6/4/12 page 95 confidential v5 ddr_dq15 i/o sdram data bits [15:0] t5 ddr_dq14 i/o t8 ddr_dq13 i/o u8 ddr_dq12 i/o v8 ddr_dq11 i/o u7 ddr_dq10 i/o t6 ddr_dq9 i/o u5 ddr_dq8 i/o t2 ddr_dq7 i/o t4 ddr_dq6 i/o t1 ddr_dq5 i/o u2 ddr_dq4 i/o v4 ddr_dq3 i/o u4 ddr_dq2 i/o v2 ddr_dq1 i/o u1 ddr_dq0 i/o v7 ddr_dqm1 o data mask for byte lane 1 v1 ddr_dqm0 o data mask for byte lane 0 u6 ddr_dqs1 i/o data strobe for for byte lane 1 u3 ddr_dqs0 i/o data strobe for for byte lane 0 v6 ddr_dqs1n i/o data strobe complement for byte lane 1 v3 ddr_dqs0n i/o data strobe complement for byte lane 0 p2 ddr_rasn o row access strobe t7 ddr_vref1 a this pin should be set to ? of vdd (0.9v) for ddr2 t3 ddr_vref0 a this pin should be set to ? of vdd (0.9v) for ddr2 r3 ddr_wen o write enable control table 6-33. ddr2 sdram signals pin primary function description name type
max64180 data sheet pin definitions revision 1.1 6/4/12 page 96 confidential 6.4.6 usb signal group the usb signal group consists of eight signals to support a usb 2.0 high-speed interface, a host or device interface ( ta b l e 6 - 3 4 ). these signals are in the usb power domain. 6.4.7 uart signal group ta b l e 6 - 3 5 shows the universal asynchronous receiver tr ansmitter (uart) signal group. these signals are in the host power domain. table 6-34. usb signals pin primary function description name type f17 usb_ana_tst a connect this signal to gnd. test mode signal for the usb analog sections. h18 usb_dm a usb d- signal j18 usb_dp a usb d+ signal g18 usb_vbus a separate 5.0v supply for usb g17 usb_id a this signal differentiates a mini-a fr om a mini-b plug. the id detector senses the id line?s state to indicate which ty pe of plug is connected. the id detector can differentiate the following conditions: id pin floating (>100kohm) = the connected plug is a mini-b plug. id pin shorted to ground (<10ohms) = the connected plug is a mini-a plug. h17 usb_rext a external 3.4kohm 1% resistor connection that sets the bias current for the usb phy e18 usb_xin a crystal oscillator xi pin. connects a 12mhz oscillator f18 usb_xo a crystal oscillator xo pin. connects a 12mhz oscillator table 6-35. uart signals pin primary function alt. description name type b11 uartd_rxd i mme_rxd debug uart received data 1 1.the debug uart port is useful in debugging the syst em and should always be connected to the serial terminal. the alternate functions mme_rxd and mme_txd are selected using the dbguartsel bit in the serial i/o control register. a11 uartd_txd o mme_txd debug uart transmitted data
max64180 data sheet pin definitions revision 1.1 6/4/12 page 97 confidential 6.4.8 spi/bitstream signal group ta b l e 6 - 3 6 shows the serial peripheral interface/bitstream (bs) signal group. these signals are in the host power domain. 6.4.9 twi signal group ta b l e 6 - 3 7 shows the i 2 c compatible two-wire interface (twi) signal group. these signals are in the host power domain. table 6-36. serial peripheral interface/bitstream interface signals pin primary function alt. function description name type a12 spi_mclk i/o bs_clk 1 1. the alternate function bs_clk, bs_data, bs_en, and bs_req are selected using bits in the serial i/o control register. spi master clock bitstream clock a14 spi_miso i/o spi master in/slave out b13 spi_mosi i/o bs_data spi master out/slave in bitstream data b14 spi_mss0 i/o bs_en spi master/slave select 0 bitstream data enable a13 spi_mss1 i/o bs_req spi master/slave select 1 bitstream data request table 6-37. two-wire interface signals pin primary function alt. function description name type b12 twi0_scl iod twi1_scl 1 1. the alternate functions twi1_scl and twi1_sda are selected using the twi1cfg bit in the serial i/o control register. twi serial clock c11 twi0_sda iod twi1_sda twi serial data
max64180 data sheet pin definitions revision 1.1 6/4/12 page 98 confidential 6.4.10 pwm signal group ta b l e 6 - 3 8 shows the pulse width modulator (pwm) signal group. these signals are in the host power domain. 6.4.11 gpio signal group the gpio signal group has four signals as shown in ta b l e 6 - 3 9 . they are dedicated general purpose input/output (gpio) signals. th ese dedicated gpio signals are all in the host power domain. the i/o pins in the gpio signal group have progra mmable 15kohm 20% pull-up and pull-down resistors. the pull-up resistors are enabled by default and can be disabled using the associated bit in the gpio 0 pull-up enable register. the pull-down resistors are disabled by default and can be enabled using the gpio 0 pull-down enable register. there are 20 other gpio signals that are multiplexed wit h other signals. these pins can be used as gpio pins when their primary or alternate functions (alt ) are not used. these additional gpio signals are broken into two groups as shown in ta b l e 6 - 4 0 and table 6-41 . these signals are not necessarily in the host power domain. refer to the primary signal name to check the power domain. table 6-38. pulse width modulator signals pin primary function description name type c9 pwm_0 o pulse width modulator interface table 6-39. gpio signals pin primary function gpio function description name type a9 gpio_0 i/o gpio_0_00 gpio bit [0] b9 gpio_1 i/o gpio_0_01 gpio bit [1] a10 gpio_2 i/o gpio_0_02 gpio bit [2] b10 gpio_3 i/o gpio_0_03 gpio bit [3]
max64180 data sheet pin definitions revision 1.1 6/4/12 page 99 confidential the multiplexed signals associated with gpio_1 are di sabled by default and enabled using the associated bits in the gpio 1 sel register. when enabled, the i/ o function has priority over both the primary and the alternate function (alt). the i/o pins in the gpio_1 signal group have programmable 15kohm 20% pull-up and pull-down resistors. the pull-up resistors ar e enabled by default and can be disabled using the associated bit in the gpio 1 pull-up enable register. the pull-down resistors are disabled by default and can be enabled using the gpio 1 pull-down enable register. the multiplexed signals associated with gpio_2 are enabled using the associated bits in the gpio 2 sel register. gpio_2 are enabled by default, which forc es the signals to be an input after reset. when enabled, the i/o function has priority over both the primary and the alternate function (alt). the i/o pins in the gpio_2 signal group have programmable 15kohm 20% pull-up and pull-down resistors. the pull-up resistors are enabled by default and can be disa bled using the associated bit in the gpio 2 pull-up enable register. the pull-down resistors are disabled by default and can be enabled using the gpio 2 pull- down enable register. table 6-40. gpio signals pin signal name type alternate function gpio function primary function c3 gpio_1_00 host_intn iod ? l17 gpio_1_19 vid0_field i ? t16 gpio_1_21 aud0_spdif o ? table 6-41. addition al gpio signals pin signal name type alternate function gpio function primary function m16 gpio_2_00 vid0_hsync i ? l16 gpio_2_01 vid0_vsync i ? k17 gpio_2_03 cfg ? e16 gpio_2_06 ? i/o c18 gpio_2_07 ? i/o d16 gpio_2_08 ? i/o a18 gpio_2_09 vid2_field i/o ? b15 gpio_2_10 vid2_hsync i/o ? b16 gpio_2_11 vid2_vsync i/o ? a14 gpio_2_16 spi_miso i/o ? b14 gpio_2_17 spi_mss0 i/o bs_en a13 gpio_2_18 spi_mss1 i/o bs_req a12 gpio_2_19 spi_mclk i/o bs_clk b13 gpio_2_20 spi_mosi i/o bs_data b12 gpio_2_21 twi0_scl iod twi1_scl c11 gpio_2_22 twi0_sda iod twi1_sda c9 gpio_2_29 pwm_0 o ?
max64180 data sheet pin definitions revision 1.1 6/4/12 page 100 confidential 6.4.12 jtag signal group the jtag signal group has seven signals as shown in ta b l e 6 - 4 2 . these signals are in the aud power domain. 6.4.13 configuration the configuration signal group has two signals as shown in ta b l e 6 - 4 3 . these signals are in the vid0 power domain. the configuration mode is determined during device boot-up. see ?boot mode for the mmes and the arm? for more information. table 6-42. jtag signals pin primary function description name type r17 jtag_tap_sel i this signal is used to select between the arm tap controller and the test mode tap controller. 0: arm debugger 1: boundary scan t17 test i when set to 1, the chip is placed in test mode v17 jtag_tck i jtag test clock u17 jtag_tdi i jtag test data input u18 jtag_tdo o jtag test data output v18 jtag_tms i jtag test mode select t18 jtag_trstn i jtag test reset active low table 6-43. configuration signals pin primary function description name type k17 cfg i 0: spi eeprom 1: xmodem k16 host_cfg_0 i 0: parallel slave 1: master
max64180 data sheet pin definitions revision 1.1 6/4/12 page 101 confidential 6.4.14 clock the clock signal group has two signals as shown in ta b l e 6 - 4 4 . these signals are in the host power domain. see ?clock and pll inputs? on page 52. 6.4.15 reset the reset signal group has one signal as shown in ta b l e 6 - 4 5 . this signal is in the aud power domain. table 6-44. clock signals pin primary function description name type f1 clk_in i clock input f2 clk_sel i selects the source clock for the plls to come from either the usb oscillator or clk_in. 0: usb oscillator 1: external clk_in table 6-45. reset signals pin primary function description name type r16 resetn i active low chip reset
max64180 data sheet pin definitions revision 1.1 6/4/12 page 102 confidential 6.4.16 power and ground pins table 6-46. power pins pin signal name function voltage t14 aud_vdd power for audio circuitry 1.8, 2.5, 3.3v u14 aud_vdd v14 aud_vdd e8 core_vdd power for core logic 1.05v e9 core_vdd e10 core_vdd e11 core_vdd e12 core_vdd e13 core_vdd e14 core_vdd h5 core_vdd p9 core_vdd power for core logic 1.05v p10 core_vdd p11 core_vdd p12 core_vdd p13 core_vdd p14 core_vdd t13 core_vdd u13 core_vdd v13 core_vdd c8 gnd common ground ? c10 gnd c12 gnd g1 gnd g2 gnd g3 gnd g5 gnd g7 gnd g8 gnd g9 gnd
max64180 data sheet pin definitions revision 1.1 6/4/12 page 103 confidential g10 gnd common ground ? g11 gnd g12 gnd h7 gnd h9 gnd h10 gnd h12 gnd j7 gnd j8 gnd j9 gnd j10 gnd common ground ? j11 gnd j12 gnd j14 gnd k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 gnd l7 gnd common ground ? l9 gnd l10 gnd l12 gnd m7 gnd m8 gnd m9 gnd m10 gnd m11 gnd m12 gnd t12 gnd u12 gnd v12 gnd table 6-46. power pins pin signal name function voltage
max64180 data sheet pin definitions revision 1.1 6/4/12 page 104 confidential c6 host_vdd power for host processor 3.3v e5 host_vdd e6 host_vdd e7 host_vdd f5 host_vdd f3 pll_vdd power for phase lock loop 1.05v h1 ddr_vdd power for ddr memory controller 1.8v h2 ddr_vdd h3 ddr_vdd j3 ddr_vdd j5 ddr_vdd k5 ddr_vdd l5 ddr_vdd m5 ddr_vdd n5 ddr_vdd p5 ddr_vdd p6 ddr_vdd p7 ddr_vdd p8 ddr_vdd 1.8v t9 ddr_vdd t10 ddr_vdd t11 ddr_vdd u11 ddr_vdd v11 ddr_vdd f14 usb_dvdd digital power for usb port 1.05v h14 usb_avdd power for usb port 3.3v h16 usb_avdd j16 usb_avdd j17 usb_avdd k18 usb_avdd d18 usb_gnd ground for usb port ? e17 usb_gnd f16 usb_gnd g14 usb_gnd g16 usb_gnd table 6-46. power pins pin signal name function voltage
max64180 data sheet pin definitions revision 1.1 6/4/12 page 105 confidential 6.5 pin list by power group ta b l e 6 - 4 7 shows the signals associated with each of the power domains. k14 vid01_vdd power for video port 0 1.8, 2.5, 3.3v l14 vid01_vdd m14 vid01_vdd n14 vid01_vdd c13 vid23_vdd power for video port 2 1.8, 2.5, 3.3v c14 vid23_vdd table 6-47. signal group names interface power domain voltage signals host host 3.3v host_a[6:1], host_d[15:0], host_cs0n, host_dmarq, host_intn, host_ren, host_waitn, host_wen uart uartd_rxd, uartd_txd spi/bitstream spi_mclk, spi_miso, spi_mosi, spi_mss0, spi_mss1 twi twi0_scl, twi0_sda pwm pwm_0 gpio gpio_[0:3] 1 gpio_1_00 gpio_2_16, gpio_2_17, gpio_2_18, gpio_2_19, gpio_2_20, gpio_2_21, gpio_2_22, gpio_2_29 clk clk_in, clk_sel audio aud 1.8, 2.5, 3.3v aud0_bck, aud0_idat, aud0_lrck, aud0_mclk, aud0_odat0, aud0_spdif reset resetn gpio gpio_1_21 jtag 3.3v jtag_tap_sel, test, jtag_tck, jtag_tdi, jtag_tdo, jtag_tms, jtag_trstn core core 1.05v no core signals are brou ght out directly to the i/o pins. ddr ddr 1.8v ddr_padhi, ddr_padlo, ddr_a[12:0], ddr_ba[1:0], ddr_casn, ddr_cke, ddr_clk0, ddr_clk0n, ddr_csn, ddr_dq[15:0], ddr_dqm[1:0], ddr_dqs[1:0], ddr_dqsn[1:0], ddr_rasn, ddr_vref1, ddr_vref0, ddr_wen usb usb 3.3v usb_ana_tst, usb_dm, usb_dp , usb_id, usb_rext, usb_xin, usb_xo 5.0v usb_vbus table 6-46. power pins pin signal name function voltage
max64180 data sheet pin definitions revision 1.1 6/4/12 page 106 confidential 6.5.1 hookup recommendations wh en interfaces are unused ta b l e 6 - 4 8 shows the hookup recommendations when some of the interfaces are unused. the pull-up/pull- down column indicates: ? up: the pin has the internal pull-up enabled at power-on/reset. ? down: the pin has the internal pull-down enabled at power-on/reset. ? dis: the pin has pull-up/pull-down control, but they are disabled at power-on/reset. ? none: the pin has no control over pull-up/pull-down. the default column indicates the state of the pin at reset: ? 0: the pin is driven to 0. ? 1: the pin is driven to 1. ? 0(p): the pin is pulled by a resistor to a value of 0. ? 1(p): the pin is pulled by resistor to a value of 1. ? hi-z: the pin is not driven. ? ?: the pin is an input only and must be driven. ? nc: the pin is a no connect (leave it unconnected). note: memory (ddr2 sdram) and power pins are not included in this list, since they must always be connected for the device to operate correctly. this also applies when the usb block is not used on the max64180. video vid0 1.8, 2.5, 3.3v vid0_d[7:0], vid0_field, vid0_hsync, vid0_outclk, vid0_pixclk, vid0_vsync configuration cfg cfg, host_cfg_0 gpio gpio_1_19, gpio_2_00, gpio_2_01, gpio_2_03 video vid2 1.8, 2.5, 3.3v vid2_d[7:0], vid2_field, vid2_hsync, vid2_pixclk, vid2_vsync gpio gpio_2_09, gpio_2_10, gpio_2_11, gpio_2_06, gpio_2_07, gpio_2_08 1. only gpio_0_[3:0] are dedicated gpios; all other gpio signals are multiplexed with other signals listed in table 6-47 . for example, the primary function of gpio_1_00 is a ?host interrupt.? see table 6-40 and table 6-41 for a detailed description. table 6-47. signal group names interface power domain voltage signals
max64180 data sheet pin definitions revision 1.1 6/4/12 page 107 confidential internal pull-up and pull-down values are 15kohm 20%. table 6-48. hookup recommendations when interfaces are unused pin name dir pad type pull-up/ pull-down default recommendation if the interface is not used video_port 0 vid0_d7 i i input_only none ? gnd vid0_d6 i i input_only none ? gnd vid0_d5 i i input_only none ? gnd vid0_d4 i i input_only none ? gnd vid0_d3 i i input_only none ? gnd vid0_d2 i i input_only none ? gnd vid0_d1 i i input_only none ? gnd vid0_d0 i i input_only none ? gnd vid0_field i io gpio up 1(p) nc, pulled up by default vid0_hsync i io gpio up 1(p) nc, pulled up by default vid0_outclk o o output_only none hi?z nc vid0_pixclk io io none hi?z gnd vid0_vsync i io gpio up 1(p) nc, pulled up by default vid2_d7 io io none hi?z nc, configure as output after reset vid2_d6 io io none hi?z nc, configure as output after reset vid2_d5 io io none hi?z nc, configure as output after reset vid2_d4 io io none hi?z nc, configure as output after reset vid2_d3 io io none hi?z nc, configure as output after reset vid2_d2 io io none hi?z nc, configure as output after reset vid2_d1 io io none hi?z nc, configure as output after reset vid2_d0 io io none hi?z nc, configure as output after reset vid2_field io io gpio up 1(p) nc, pulled up by default vid2_hsync io io gpio up 1(p) nc, pulled up by default vid2_pixclk io io none hi?z nc, configure as output after reset vid2_vsync io io gpio up 1(p) nc, pulled up by default
max64180 data sheet pin definitions revision 1.1 6/4/12 page 108 confidential usb 1 usb_ana_tst a io nc usb_dm a io nc usb_dp a io nc usb_vbus a io nc usb_id a io nc usb_rext a io usb_avdd usb_xin a io nc usb_xo a io nc audio aud0_bck io io none hi?z nc, configure as output after reset aud0_idat i i gpio (input_only) none hi?z gnd aud0_lrck io io none hi?z nc, configure as output after reset aud0_mclk io io none hi?z nc, configure as output after reset aud0_odat0 o o output_only none 0 nc aud0_spdif o io gpio up 0 nc pwm pwm_0 o io gpio up 1 nc gpio gpio_0 io io gpio up 1(p) nc gpio_1 io io gpio up 1(p) nc gpio_2 io io gpio up 1(p) nc gpio_3 io io gpio up 1(p) nc twi twi0_scl io io gpio up 1(p) nc, pulled up by default twi0_sda io io gpio up 1(p) nc, pulled up by default spi spi_mclk io io gpio up 1(p) nc, pulled up by default spi_miso io io gpio up 1(p) nc, pulled up by default table 6-48. hookup recommendations when interfaces are unused pin name dir pad type pull-up/ pull-down default recommendation if the interface is not used
max64180 data sheet pin definitions revision 1.1 6/4/12 page 109 confidential spi_mosi io io gpio up 1(p) nc, pulled up by default spi_mss0 io io gpio up 1(p) nc, pulled up by default spi_mss1 io io gpio up 1(p) nc, pulled up by default uart uartd_rxd i i input_only none ? hook up to dbg_txd uartd_txd o o output_only none 1 hook up to dbg_rxd host host_a6 o io none hi?z gnd host_a5 o io none hi?z gnd host_a4 o io none hi?z gnd host_a3 o io none hi?z gnd host_a2 o io none hi?z gnd host_a1 o io none hi?z gnd host_cs0n o io none 1 nc host_d15 io io none hi?z gnd host_d14 io io none hi?z gnd host_d13 io io none hi?z gnd host_d12 io io none hi?z gnd host_d11 io io none hi?z gnd host_d10 io io none hi?z gnd host_d9 io io none hi?z gnd host_d8 io io none hi?z gnd host_d7 io io none hi?z gnd host_d6 io io none hi?z gnd host_d5 io io none hi?z gnd host_d4 io io none hi?z gnd host_d3 io io none hi?z gnd host_d2 io io none hi?z gnd host_d1 io io none hi?z gnd host_d0 io io none hi?z gnd host_dmarq i io none 0 gnd table 6-48. hookup recommendations when interfaces are unused pin name dir pad type pull-up/ pull-down default recommendation if the interface is not used
max64180 data sheet pin definitions revision 1.1 6/4/12 page 110 confidential host_intn i io up 1(p) gnd host_ren o io none 1 nc host_waitn i io none hi?z gnd host_wen o io none 1 nc host_cfg_0 i i input_only none 0 gnd cfg i io gpio up 1(p) nc, pulled up by default jtag jtag_tap_sel i i input_only none 1 gnd test i i input_only none 0 gnd jtag_tck i i input_only up 1(p) gnd jtag_tdi i i input_only up 1(p) hook up to test_tdo jtag_tdo o o output-only up 1(p) hook up to test_tdi jtag_tms i i input_only up 1(p) gnd jtag_trstn i i input_only up 1(p) gnd clock clk_in i i input_only gnd 1. when the usb block is not used, in addition to connecting the usb pins as recommended in table 6-48 , the usb vdd pins still must be connected to their standard s upply levels, as shown below: - usb_dvdd 1.05 v - usb_avdd 3.3 v - usb_acvdd 3.3 v table 6-48. hookup recommendations when interfaces are unused pin name dir pad type pull-up/ pull-down default recommendation if the interface is not used
max64180 data sheet package information revision 1.1 6/4/12 page 111 confidential 7 package information the max64180 is available in a lead(pb)-free package. the max64180 is a 248-pin, chip scale thin ball grid array (ctbga) package with a 10mm 10mm footprint and 0.5mm pin pitch. lead(pb)-free products from maxim comply with the te mperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. this section provides the package outline for the max64180 device. for the latest package outline info rmation and land patterns, go to www.maxim-ic.com/packages . package type package code document no. ctbga x24800+1 90-0352 , 21-0503
max64180 data sheet package information revision 1.1 6/4/12 page 112 confidential 7.1 package outline?248-pin ctbga, 10mm 10mm figure 7-41 illustrates the package outline for the max64180 device. the ou tline contains the top view, bottom view, and side view. 7.2 package diagram figure 7-41. max64180 248-pin ctbga package physical drawing units=mm units=mm
max64180 data sheet package information revision 1.1 6/4/12 page 113 confidential 7.3 thermal data table 7-49 shows the case thermal conductivity data for the max64180 248-pin ctbga package using jesd51-7 standard. 7.3.1 thermal resistance the thermal resistance of any device is dependent on the board size. figure 7-42 shows how the thermal resistance of max64180 varies from the standard jedec board size to small boards used in camera applications. it is recommend ed that for small form factor boards, connect the device and the board to the system chassis to dissipate the heat of the device and the board. figure 7-42. thermal resistance note : contact your local maxim repr esentative for more details. table 7-49. case thermal conductivity data symbol parameter value ? ja junction to ambient 20.7c/watt ? jt junction to case 4.2c/watt t jmax maximum junction temperature 125c t amax maximum ambient temperature 70c t amin minimum ambient temperature 0c
max64180 data sheet package information revision 1.1 6/4/12 page 114 confidential 7.4 marking 1. product name: MAX64180CXO+ 2. date and revision: yy-year, ww-week, xx-chip revision of die which is a1 3. lot number: nnn-nu mber, ll-letter 4. manufactured at: taiwan figure 7-43. max64180 marking MAX64180CXO+ yywwa1 nnnll taiwan pin 1
max64180 data sheet ordering information 116 revision 1.1 6/4/12 page 115 confidential 8 ordering information table 8-50 describes the ordering information for the max64180 device. table 8-50. ordering information part order number description MAX64180CXO+ lead(pb)-free, 248-pin, ctbga package with a 10mm 10mm footprint, 0.5mm ball spacing
max64180 data sheet ordering information 116 revision 1.1 6/4/12 page 116 confidential

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